Dear all,
I come to you with an error injection problem in the L2 cache of a T1040-e5500 core.
I have to do such sequence for safety reasons (need to ensure that the HW is good before executing SW on top of it), and I get strange results.
Here is my error injection sequence:
L1D and L1I cache are not activated
L2 cache is active with L2DO=1, so no code is fetched in L2.
r3 = 0x55540028
dcbtls 2, 0, r3 * Get the data at 0x55540028 in L2 (in fact the whole cache line i.e. 64 bytes from 0x55540000)
L2ERRCTL[L2CTHRESH] = 1 * Report an error condition once one single bit error is detected
L2ERRCTL[L2CCOUNT] = 0 * Reset single bit error counter
L2ERRINJCTL[DERRIEN] = 1 * Activate single bit data error injection
L2ERRINJCTL[ECCERRIM] = 0 * Do not corrupt ECC
L2ERRINJLO = 1 * Corrupt data bit 63
L2ERRINJHI = 0
std r3, 0(r3) * Data at 0x55540028 is written, and so corrupted
L2ERRINJCTL = 0 * Deactivate error injection
lwz r4, 0(r3) * Read the data ==> this is where the error is detected
Note that according to e5500 RM, each mtspr L2ERR* is preceded by msync + isync, and followed by isync. So no error is supposed to be injected anywhere else.
Once here, I get the following error registers set:
L2ERRDET = 4 * SBECCERR = 1, which means "Data ECC error detected" - OK
L2CAPTECC = 0x07000000 * The calculated ECC syndrome (ECCSYND = 7) is not eqal to the stored ECC syndrome (ECCCHKSUM = 0) of the captured error - OK
L2ERREADDR = 0
L2ERRADDR = 0x55540020 * Is supposed to be the real address of a captured error detected in the L2 cache. In fact it seems to be the real address of the corrupted data bitwise anded with ~0x1F, so the address of the cache line, or the address of the second half part of that cache line where the error has happened.
L2ERRATTR = 0x70112001 * Here again, DWNUM part (here 0x7) is supposed to be the doubleword number of the detected error, but whatever the error address is, I always get
- DWNUM=3 if the error address is between 0xzzzzzz00 and 0xzzzzzz1F
- DWNUM=7 if the error address is between 0xzzzzzz20 and 0xzzzzzz3F
It is a bit annoying, but I can figure out this is related to SECDED implementation. Am I right.
L2CAPTDATAHI = 7
L2CAPTDATALO = 9 * It is also annoying, because this is the doubleword data at the end of the cache line, which is not supposed to be corrupted!
L2ERRCTL[L2CCOUNT] = 2 * And finally, it seems that I'm throwing 2 ECC single-bit errors where I'm only expecting one
So the big question is: is it the normal and expected behavior towards the e5500 SECDED implementation, or am I doing something wrong with my error injection sequence.
Thanks for any help or idea
Regards
Christophe
