How secondary core boots in T2080 processor

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How secondary core boots in T2080 processor

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Contributor II

Hi,

I am working on a board which requires a AMP system. The board is designed with T2080 PPC processor. My requirement is to run the system with two different OS. Linux on core0 and vxWorks on core1. I have the context of booting from core0 perspective. Core0 act as primary core during power ON reset. When processor comes out of reset, default 4KB of boot space is already mapped for all cores, but all the cores are on boot hold-off state except core0. So core0 starts the execution from reset vector address 0xfffffffc. The reset vector address is mapped to boot rom NOR flash, from where uboot is loaded and control transfer to linux kernel. I am interested to know

1. how I can allow the core1 to boot with other OS(vsWorks)?

2. What will be reset vector address for core1 when it is released from boot-holf state, at that time no MMU/TLB initialized for core1. Only 4KB boot page is visible to core1 and that too mapped to NOR flash which have the uboot image?

Thanks in advance.QorIQ Processing Platforms

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3 Replies

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Contributor III

Hi Ravi,

OS is executed by bootloader. Would it be fine for other cores to reach to bootloader point and then execute respective OS? A more appropriate solution would be to use Hypervisor. In that case the Hypervisor will run after bootloader and also it can give you a lot of possibilities to partition your system.

Regards,

Adeel

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NXP TechSupport
NXP TechSupport

Hello Ravi Kumar,

You could consider to use boot space translation mechanism, the boot space translation can be set up by an external host when the device is configured to be in boot hold off mode.

When each core comes out of reset, its MMU has one 4KB page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at the effective address 0x0_FFFF_FFFC.

 

To boot space translation mechanism allows translation of this window(in physical address space) to one specified by BSTRH, BSTRL and BSTAR. Processor will fetch first instruction from effective address 0xFFFF_FFFC as usual, the boot space translation mechanism will translate the physical address to the specific address such as 0x6_0000_0FFC.


Have a great day,
TIC

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Contributor II

Thanks Yping.

But still I am struggling to find answer for second question.

2. What will be reset vector address for core1 when it is released from boot-holf state, at that time no MMU/TLB initialized for core1. Only 4KB boot page is visible to core1 and that too mapped to NOR flash which have the uboot image for core0?

Which memory region should BSTRH and BSTRL should point? During boot hold-off state, No memory mapping has done in core1 TLB's. So I may assume core1 can't access core0's memory mapped region.

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