I would like to test the single-bit parity check detection on L1 data cache of the T2080 SoC containing e6500 core. For this purpose I set some bits in the L1CSR0 as recommended in the EREF and e6500 reference manuals in order to enable parity check and parity fault injection. According to the manuals, once a DCP_ERROR is raised in the MCSR, a machine check routine is executed and the address of the function to be executed once the interrupt is raised is should be specified in IVPR+IVOR1 registers. I follow instructions of reference manuals and could not make it works. In fact, the processor is stuck within the machine check routine and loops on the machine check routine despite the rfmci instruction (which is not executed because of new coming exception while being in the machine check handler). Please could someone have : 1. Some hint on why the processor is stuck and loops on the machine check error routine ? 2. An example of assembly code which detects single-bit parity error, process the error and returns back to the main function?
Here is a example of the assembly code I wrote :
L1_Parity_Test: /*Setting the interrupt vector*/ LOAD_REG_32(r5, parity_error_check_vector) mtspr CPU_PPC_E500_IVPR, r5
xor r4, r4, r4 LOAD_REG_32(r4, parity_error_check_vector) mtspr CPU_PPC_E500_IVOR1, r4 /*Enabling Machine Check MSR[ME] ans MSR[RI]*/ xor r4, r4, r4 li r4, 0x1 li r5, 0xC slw r6, r4, r5 xor r4, r4, r4 li r4, 0x2 or r6, r6, r4 sync isync mtmsr r6 isync /*Enabling Parity detection and data cache error injection type*/ LOAD_REG_32(r5, CPU_PPC_E500_L1CSR0_CE | CPU_PPC_E500_L1CSR0_CPE | CPU_PPC_E500_L1CSR0_CEI) mfspr r4, CPU_PPC_E500_L1CSR0 or r4, r4, r5 sync isync mtspr CPU_PPC_E500_L1CSR0, r4 isync
/*Disabling Machine Check MSR[ME]*/ xor r4, r4, r4 sync isync mtmsr r4 isync /*Re-enabling L1 data cache*/ LOAD_REG_32(r5, CPU_PPC_E500_L1CSR0_CE | CPU_PPC_E500_L1CSR0_CPE) mfspr r4, CPU_PPC_E500_L1CSR0 or r4,r4,r5 mtspr CPU_PPC_E500_L1CSR0,r4 /*Updating the address of the next instruction to be executed before the interrupt occurs*/ sync isync mtspr CPU_PPC_E500_MCSRR0, r0 isync