I am designing a T1042 based custom board and I have use discrete RAM chips on my board. For routing of these RAMs, I am following AN3940 "Hardware Design guidelines for DDR3". I n this document there is point that states:
"Ensure differential termination is used for DDR differential clocks", however I have used same single ended termination scheme as used in other DDR3 signals.
I am verifying my design b simulating it using Hyperlynx DDR3 batch simulations. My simulation results are passed in this case.
My question is whether it is necessary to use differential termination or it can work with single ended termination scheme?
