Hi, I’m interested in using instructions for data cache locking. From the manual I saw there are instructions like dcbtls or dcblc for locking or unlocking cache lines. My idea is: suppose a core wants to use the variable y, before using y the core finds the address of y and it uses the instruction dcbtls for locking the cache line specified by the address found before.
I have another question: how these instructions impact the allocation of data in the shared cache?
Could you clarify what core is in question?
I'm referring to nxp t1040 platform, e5500 core. Each core should perform the procedure described above. This mechanism would serve me to provide predictable code behavior