Alternatives for CPLD while designing custom board using LS1028A

[sreedharmahadevan]

Hello all,

We are trying to develop a custom PCB similar to the LS1028A reference board but with slightly reduced peripherals. While doing the same, we encountered the CPLD and understood its role from the reference board's reference manual:

• Reset assertion to processor and devices
• Processor and system configuration
• Interrupt management
• System alert monitoring and status display
• Remapping of system boot devices
• Handling of board control and status registers

I downloaded the Verilog design files corresponding to the CPLD but could not fully understand its flow and so not able to correlate to the above points. I saw some similar posts but nothing pertained to what I wanted to know, and so I would like to know the exact reasoning behind choosing a CPLD to do the above job. Why was a CPLD chosen and why not a Microprocessor or a Microcontroller?

If I wanted to replace the CPLD with a Microcontroller, is that even possible to achieve the Reset sequencing and other activities using that? If yes, what extra should I take care of and what kind of approach is needed here?

[sreedharmahadevan]

Thanks a lot for your response.

[ufedor · Accepted solution]

You wrote:

> Why was a CPLD chosen and why not a Microprocessor or a Microcontroller?

Because it is the most straightforward solution capable to implement the mentioned functionality.

> If I wanted to replace the CPLD with a Microcontroller,

> is that even possible to achieve the Reset sequencing and other activities using that?

Theoretically it is possible.

> what extra should I take care of and what kind of approach is needed here?

Just implement the reset sequence with timings specified in the QorIQ LS1028A/LS1018A Data Sheet, 3.7 Reset initialization timing specifications and DDR SDRAM reset as it is described in the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM.