You wrote:
> During these transaction, whether,core will stop its normal
> cycle and reads the port data and writes to DDR2? /is core
> intervention required to write PCIe data to DDR2 or not?.
The core operation will not be interrupted - i.e. PCI Express transactions targeting MPC8548 inbound ATMU with translation to DDR2 SDRAM region are converted to direct memory write operations by the PCI Express interface.
Best regards,
Fedor
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