MPC8313 GPCM LOEn, LWEn timings

[wonderwizard]

Hi,

I am checking some timing for constraints for my FPGA to MPC8313 interface. It looks to me like these two references disagree on the behavior of LWE and LOE with respect to LCLK.

REF 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Figure 10-35 shows LWE falling on the rising edge of LCLK, the table 10-33 lists lots of tAWE options but the minimum is '1'.

REF 2 MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4  Table 45 / Figure 37 / Figure 38 shows the LOE LWE signals as launched from the MPC8313 on the falling edge of LCLK.

Perhaps my interpretation is wrong? Any help would be much appreciated.

Thanks

[LPP · Accepted solution]

The MPC8313 device has similar local bus controller as in other MPC83xx processors. This controller provides support for delay-locked loop (DLL) with software-configurable bypass for low frequency bus clocks. DLL is enabled to work at high frequency. If you look at MPC8379 Hardware Specifications, you will see two different cases – “DLL enabled” and “DLL bypass”. In DLL enabled mode all timings are measured from rising edge, whereas in “DLL bypass” mode these timings are specified from falling edge.

http://cache.freescale.com/files/32bit/doc/data_sheet/MPC8379EEC.pdf

Detailed description of DLL bypass mode is provided in Section 10.4.1.7 of MPC8379ERM

http://cache.freescale.com/files/32bit/doc/ref_manual/MPC8379ERM.pdf

In contrast to MPC8379, MPC8313 local bus is specified to operate at low frequency only (<67MHz). The DLL is always disabled in MPC8313. Corresponding signals (LSYNC_IN,LSYNC_OUT) and control bits has been removed from the design. MPC8313 Hardware Specifications shows timing diagrams for DLL bypass mode only. Unfortunately, the Reference Manual was not properly modified for this case.

[wonderwizard]

Many Thanks.