Critical Interrupt Exception [MPC8270]

[ManjulaMankar]

We are trying to port the software of MPC8250 to MPC8270. Since, Critical Interrupt Exception (0x00A00)—G2_LE is part of MPC8270 only and not part of MPC8250. I have a question here.

The following events occur when the G2_LE recognizes the assertion of core_cint(Core Critical Interrupt):

• Multi-cycle instructions not in the completion stage are terminated.
• Outstanding load or store instructions that have not been completed are terminated
• Any outstanding page table search activity is terminated

I would like to know what happens if the above events occur in MPC8250? How is it handled as we don't have core_cint signal in MPC8250 G2 core?

Which exception is raised for these events as we don't have critical interrupt exception in MPC8250?

Please share your thoughts.

[ArchibaldBruce]

If you need any free samples of MPC8270 series products, you can follow this to reach Ersa Electronics.

[Hector_Villarruel]

Hello @ManjulaMankar 

This post is to inform you that we acknowledge the receipt of your case,
I Keep working on the solution on this case.
I’ll keep you informed on the process,

Have a great day.

BR,

Hector

[ManjulaMankar]

Hi Hector,

Do you have any updates on the query which I had asked.

Thanks,

Manjula.

[Hector_Villarruel]

Hello @ManjulaMankar 

We apologize for the delay regarding this situation,

Regarding your question:

I would like to know what happens if the above events occur in MPC8250? How is it handled as we don't have core_cint signal in MPC8250 G2 core?

Is treated in the same way that is handled by the MPC8250 due that the MPC8250 and MPC8270 has the same G2 Core and same CPM.

Have a great day.

[ManjulaMankar]

Thanks for the response. In the documents which I had referred MPC8250 and MPC8270 doesn't have the same G2 Core. MPC8250 is of family MPC8260 and MPC8270 is of family MPC8280. PFA.

[Hector_Villarruel]

Hello @ManjulaMankar 

Hope this post finds you well,

Regarding your main question,

The G2 Core will handle the external interrupt using MSR[EE] , nevertheless instead of G2_LE Core, there is not an instruction to make a return .

We would like to inform you that regarding the G2 core Reference Manual,

Table 1-6. Differences Between G2 and G2_LE Cores

G2 Core:

Only one external interrupt signal (core_int)

G2_LE Core:

An additional input interrupt signal, core_cint, implements a critical interrupt function.

Impact: MSR[CE] is allocated for enabling the critical interrupt

G2_LE Core:

A new instruction is implemented for critical interrupt

Impact: 

Return from Critical Interrupt (rfci) is implemented to return from these exception handlers.

In addition, please refer to the following statement:

8.3.9.1 External Interrupt (core_int)—Input
Following are the state meaning and timing comments for the core_int input.
State Meaning

Asserted—The core initiates an interrupt exception if MSR[EE] is set; otherwise, the core ignores the interrupt. To guarantee that the core takes the external interrupt, core_int must be held asserted until the core takes the interrupt. Negated—Indicates that normal operation should proceed. See Section 9.7.1, “External Interrupts.”
Timing Comments

Assertion—May occur at any time and may be asserted asynchronously to the input clocks. The core_int input is level-sensitive. Negation—Should not occur until the external interrupt exception is taken.

Have a great day.

BR,

Hector Villarruel

[ManjulaMankar]

Thank you for the response.