Hello NXP Experts,
Currently, I am working on the custom board which involves a Discrete DDR3L (MT41K512M16VRN-107 IT:P) interface with T2081. I have some questions regarding the DDR3L memory interface on T2081.
I have configured the .rcw, .tcl, .bin file as per the T2080RM.
1. I created the new project and then selected the "T2081QDS_init_sram -2.tcl" file for debugging the project. I have attached the .tcl file below.
2. I can debug successfully and flash on NOR devices as well.
3. Now I want to run DDR and initialize the DDR for that I have made changes in the "T2081QDS_init_core.tcl" file as per the T2080RM DDR memory map and datasheet of micron (MT41K512M16VRN-107 IT:P). I have attached the file below.
4. While I am debugging the ''T2081QDS_init_core.tcl'' file that time I am facing the error: CCSProtocolPlugin : Error writing memory [CCS last error: Scan timeout ]. I have attached the screenshot below.
5. In the QCVS tool, I have configured the registers as per the datasheet and T2080RM but I am also facing an error: D_INIT was not cleared by hardware. I have attached the screenshot below.
My Concern is, where I will use ''init_core.tcl'' and ''init_sram.tcl'' files and how I will configure the DDR registers in QCVS or init_core.tcl file.
Referred Documents:
1. T2080RM Rev. 4, 04/2021
2. QCVS_DDR_User_Guide Reference Manual 4.x, 02/2016
3. T2080RDBPCUG User Guide Rev. 1, 08/2021
4. MT41K512M16VRN-107 IT:P Datasheet.
CodeWarrior information:
CodeWarrior for Power Architecture
Version: 10.5.1
Build Id:160128
Find the attached documents.
Please give your valuable support/guidance.
Thanks and regards,
Padmakar
