The PCA9450C's NVCC_3V3/BUCK4 section is being substituted for more ampacity with an external SMPS controlled by a synchronous state machine such to be enabled post NVCC_DRAM/BUCK6's voltage rise and then later disabled post NVDD_SD2/LDO5's voltage fall as per BUCK4's nominal behavior if otherwise present.
The BUCK4 section is being disabled by tying BUCK4FB to INB45 and LX's left floating per the datasheet.
The substituted 3V3 SMPS output is further gated by a PMOSFET such that insertion and disablement occur with minimal delay.
The state machine is attached as a png.
Questions: Will the absence and disablement of BUCK4 interfere with LDO5's nominal sequencing/start (its POK contribution) and halt the process? Are there any other timing issues or considerations with this substitution, power-up or power-down, or will it be transparent as intended?
