Hi,
I need to boot p2041rdb with SRIO configured, the user-guide claims I should load an RCW with serdes protocol 0x02. Is there a RCW available with the 0x02 protocol that I can use?
Best Regards,
Nora
已解决! 转到解答。
Sorry, we do not offer ready-to-use RCW values for any possible customer configurations. We expect our customers will create their own RCWs for their purposes.
Have a great day,
Alexander
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Okay, thanks for the quick reply.
I found this guide from sdk 1.9 documentation that I followed Submit Form: which for the SRA application on p2041rdb states that I should use the following RCW:
00000000: AA55 AA55 010E 0100 1260 0000 0000 0000
00000010: 241C 0000 0000 0000 0899 30C0 C7C0 2000
00000020: FE80 0000 4000 0000 0000 0000 0000 0000
00000030: 0000 0000 D003 0F07 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 57B0 F7D9
I followed the steps in the SRA guide, but I am getting this text in uboot (see bold text):
Reset Configuration Word (RCW):
00000000: 12600000 00000000 241c0000 00000000
00000010: 089930c0 c7c02000 fe800000 40000000
00000020: 00000000 00000000 00000000 d0030f07
00000030: 00000000 00000000 00000000 00000000
Board: P2041RDB, CPLD version: 4.1 vBank: 1
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM CT51264BF1339.C16F
2 GiB left unmapped
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=9, ECC off)
DDR Chip-Select Interleaving Mode: CS0+CS1
POST memory PASSED
Flash: 128 MiB
L2: 128 KiB enabled
Corenet Platform Cache: 1 MiB enabled
SERDES: bank 3 disabled
SRIO1: enabled but port error
SRIO2: disabled
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Root Complex, no link, regs @ 0xfe200000
What can cause this port error?
Yes I got SRIO working on p2041rdb by following the guide for the SRA app in the qoriq sdk. I needed to set the boards cpld's multiplexers in u-boot and also set usdpaa_mem=64M.
The cpld setting in u-boot was:
/* Especially the first one is important, there are descriptions in the datasheet of what values gives what setting. */
cpld_cmd lane_mux 6 0
cpld_cmd lane_mux a 0
cpld_cmd lane_mux c 0
cpld_cmd lane_mux d 0
cpld reset altbank /* I had a broken altbank so I did not use this command from what I remember */
Also good to keep in mind is that the usdpaa_mem boot variable cannot be larger than 64M (ie. usdpaa_mem=64M), else I couldn't use the usdpaa features...
thanks for your quick reply.
when i configure serdes as 0x11, the two srio ports configured as two 2x,
when booting show this err at u-boot
********************************
SERDES: bank 3 disabled
SRIO1: enabled but port error
SRIO2: enabled but port error
NAND: 512 MiB
***************************************
i use the u-boot 2016.1 version released by QorIQ Linux SDK 2.0,
it seems an fiexed err at function
srio_erratum_a004034() @ u-boot-2016.01-r0\arch\powerpc\cpu\mpc8xxx\srio.c
but it seems does not work.
In linux, i use usdpaa for srio and rman test, is there a good example to test doorbell?
in usdpaa-app i only found doorbell example tested with rmu, but not rman.
thanks, hope for your reply.
Sorry, we do not offer ready-to-use RCW values for any possible customer configurations. We expect our customers will create their own RCWs for their purposes.
Have a great day,
Alexander
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
(Sorry for posting double but since it didn't seem like it was visible earlier)
I found this guide from sdk 1.9 documentation that I followed Submit Form: which for the SRA application on p2041rdb states that I should use the following RCW:
00000000: AA55 AA55 010E 0100 1260 0000 0000 0000
00000010: 241C 0000 0000 0000 0899 30C0 C7C0 2000
00000020: FE80 0000 4000 0000 0000 0000 0000 0000
00000030: 0000 0000 D003 0F07 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 57B0 F7D9
I followed the steps in the SRA guide, but I am getting this text in uboot (see bold text below):
Reset Configuration Word (RCW):
00000000: 12600000 00000000 241c0000 00000000
00000010: 089930c0 c7c02000 fe800000 40000000
00000020: 00000000 00000000 00000000 d0030f07
00000030: 00000000 00000000 00000000 00000000
Board: P2041RDB, CPLD version: 4.1 vBank: 1
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM CT51264BF1339.C16F
2 GiB left unmapped
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=9, ECC off)
DDR Chip-Select Interleaving Mode: CS0+CS1
POST memory PASSED
Flash: 128 MiB
L2: 128 KiB enabled
Corenet Platform Cache: 1 MiB enabled
SERDES: bank 3 disabled
SRIO1: enabled but port error
SRIO2: disabled
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Root Complex, no link, regs @ 0xfe200000
What can cause this port error?