PD(powerdown bit) set in SRDS1_B1GCRn0

[yuchikuo]

We assigned  protocol (0x16) to configure the lanes for PCIe with SerDes on the QorIQ configuration tools. The bit settings in RCW to control the power-down are correct, and we can see the bank 1 (where the PCIe lands use) is powered. However I noticed that PD bit was set SRDS1_B1GCRn0 for lane C of Bank1, and PD bit was not set for lane D. My question is that why the Power-down bit is set in the SRDS1_B1GCRn0? Even thought the lane was not set to power-down in the RCW? If I attempt to clear the PD bit, will that put the lane in power-up state?

[r8070z]

Have a great day,

I guess you talk about P2040 device. The RCW selects a set of protocols, lane assignments and frequencies. The SOC logic translates that into per-lane and per-PLL settings on the SERDES. So the actual serdes related RCW settings are needed in order to make conclusion. Next the PD bit is writeable and can be set or cleared by the Pre-Boot Loader and software. So it is important to know when and how you noticed that PD bit was set for lane C of Bank1, and PD bit was not set for lane D.

It is supposed that lane can be powered up and down using the PD bit. Tx and Rx lane resets (by the RRST and TRST bits) are needed when power down mode is exited.

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[yuchikuo]

Hi Serguei, thank you for your reply.

The SRDS_LPD_B1 of RCW has the correct settings not to power-down the Lanes C, D, E and F but to power-down Lanes F and G via RCW[154..159] = 0b000011 for Bank 1. This is why I was surprised that the PD(powerdown bit) was set  for Lanes C and D, but not set for Lanes E and F. I saw the settings under CodeWarrior. Our code is part of booter, and no other software changed SerDes settings. (I meant to say Land E (not D) was not Powered-down in my early message)