P4080: CoreNet Coherency Fabric and Arbitration details?

[ankit7]

Case: Say, all the 8 cores in P4080 result in L1 and L2 cache miss at the same time, leading to Main memory read request with all read requests having the same timestamp

Question: How does the CoreNet Coherency fabric order arbitrate/order the requests(having the same timestamp)?
              
Could someone please guide me to the right document about CoreNet Fabric and arbitration w.r.t. Memory Controller. I could not find one.

Thanks

[marius_grigoras]

Hi,

You can take a look here [1] at 9.2 chapter, maybe this can help you. About L1 and L2 caches it's pretty hard to believe that a cache miss with the same timestamp can be generated for both L1 and L2 caches (the SoC will search the needed data consecutively starting with L1 and finishing with L3 cache).

Regards,

Marius

[1] https://freescale.securehttp.internapcdn.net/secure_freescale/ssl/secured/32bit/doc/ref_manual/P4080...

[ankit7]

Hi,

Thanks for the reply. Here is the more detailed question that is of interest w.r.t. to the application we are working on.

Assumption:
1. None of the data requested is in L1, L2 and L3 cache. But it is in Main Memory(SDRAM).

2. A core issues a read request  for 4 kB(say)  contiguous data.

3. The read request from each core is for different main memory address.

Problem Background w.r.t. P4080:

1. Asymmetric Multi-Processing(AMP) Model- Each core runs in a separate partition

2. 2 Physical Main Memory Interfaces are virtualized.

3. Each core sees a Virtual Main Memory Interface.

4. As there are 2 Physical Main Memory Interfaces, each Physical Main Memory Interface supports 4 Virtual Main Memory Interface.

Question:

     1) If the requests to access all the 8 Virtual Main memory Interfaces arrive at the same time(with the same timestamp),

          a. Are the requests queued at the Physical Main memory Interfaces? If no, what really happens at the interface?

          b. Are the requests serviced in a pre-determined order? If yes, can it be changed?

     2) The documentation [1] mentions "Read latency optimization by keeping track of owner processors”. Does it mean for the above given question (1) , the read      latencies observed by all the 8 cores will be approximately same?

It would be really helpful if you answer and provide some pointers on documentation of the same.

Thanks and regards,

Ankit

[1] P4080 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Section 9.1.1 Page 381