P2041 JTAG connection error

[avinashh]

Dear team,

I'm getting following error when trying to connect to P2041 through CWTAP.

Error launching E-core00_SRAM_P2041_Connect
CCSProtocolPlugin : Failed to reset the target
[CCS last error: p2040: Core not responding ]

Can any one what does it mean and how to fix it?

-Avinash

[avinashh]

Hi Ufedor,

Thnks for the reply. We checked the POR sequence.

The HRESET signal is not releasing after PORESET is released as per the POR sequence figure.

But in working board, HRESET is released after 100ms of PORESET release.

We programmed the CPLD once again as it generates all system required resets. but no luck.

What could be the issue. Request your support further.

--Avinash 

[ufedor]

Please refer to the 4.6.1 Power-on reset sequence, step 14 and check all previous steps.

[ufedor]

The described behaviour corresponds to the situation when the processor is unable to properly complete its POR sequence. Please refer to the QorIQ P2040 Reference Manual, Figure 4-1. Power-on reset sequence and ensure that all signals behave as described including all POR configuration signals.