What are the SVDD and XVDD current requirements for a P2020 with cfg_io_ports set to 1101. We are only using SerDes lanes 2 and 3 as SGMII. Lanes 0 and 1 are unused.
Thanks,
Todd
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> which portion is used for SVDD and which portion is used for XVDD?
The split is approximately 75% for SVDD and 25% for XVDD.
Please look at the P2020 QorIQ Integrated Processor Hardware Specifications, Table 6. I/O Power Supply Estimated Values.
Here you can find the power consumption of SERDES for different protocols. Actually XVDD (1.05 V) means here XVDD+SVDD (1.05 V).
On both P2020DS and P2020RBD we use the VDD core power 1,05V for both SVDD and XVDD.
Thank you, but is there a way to determine which portion is used for SVDD and which portion is used for XVDD?
Thanks,
Todd
> which portion is used for SVDD and which portion is used for XVDD?
The split is approximately 75% for SVDD and 25% for XVDD.