Hello, I intend to use IDT_6V49205B clock generator for P2020 but see that its rise/fall slew rate for PCIe ref_clk is too high

[stefanvranken]

The IDT_6V49205B is a programmable clock generator (IDT Versaclock-6) tailored for freescale P10xx and P20xx.

However, looking at the AC-spec of its PCIe clock output I see "Rising/Falling Edge slew rate" = 4.1 V/ns typ and 5.7 V/ns max. This is higher than max 4 V/ns edge rate of P2020 SD_REF_CLK input (P2020 hw-spec  rev3, table-76)

This seems strange because IDT_6V49205B is tailored for P20xx ?

[stefanvranken]

Feedback from IDT:

6V49205B default PCIE-clock amplitude is 800mV    (datsheet page-12: testload = 2pF, unterminated load)

P2020  SD_REF_CK input has 50 ohm-to-gnd on-chip terminator.

This reduces the amplitude in half and also reduces the slew rate in half. 5.7 v/ns becomes 2.85 v/ns.

[ufedor]

The IDT clock generator wasn't previously used in Freescale's designs.

Please address your request to the IDT support - it is possible that there is recommended connection circuit complying with the P2020 Hardware Specification requirements.

[stefanvranken]

ok, I will ask IDT