DDR_ERR_SBE
Have a great day,
P2020RDB does not support ECC for its DDR memory. You can see on the P2020RDB schematics that the P2020 DDR controllers ECC byte lane pins (MECC[0:7], MDQS8/MDQS8#) are not connected to any memory chip. Additional DDR-2 memory chip should be connected to this lane in order to keep ECC syndrome byte for each 64-bit of data in the available DDR-2 (4 x16bits) memory.
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