Trying to resolve an issue with passing an automotive battery reset spec (ISO 16750-2, section 4.6.2 reset behavior). The VBAT resets drop in 5% increments and a scenario occurs when VBAT is still above the Vuvd (2.8V) and the 3.3V under voltage is triggered due to this supply being driven by a PMIC with a 5V input. The PHY goes from Standby to Sleep mode and INH is driven low.
The only way to exit sleep mode is to disconnect VBAT completely or send activity over ethernet (since INH is connected to the 5V buck powering the PMIC). Is there a mechanism to resolve this behavior so I can pass this ISO requirement? I was thinking of something like the following:
1) Register write on power up to disable entering sleep mode by undervoltage
2) Reset IC to hold PHY in reset when VBAT drops below input spec (8ish volts), I believe INH keeps previous state when held in reset.
Anything else I should try?
Hi Petr, thanks for the response. To be clear, I don't believe we are going to power off mode as VBAT is not going below the undervoltage threshold of 2.8V as this is being driven by my power supply to replicate the ISO 16750-2 reset pulse behavior. This specific behavior occurs when VBAT is between 2.9V and 5.0V and VDDIO/VDDA/VDDD drops below 2.9V as they are supplied by the following path: VBAT -> 5V Buck -> PMIC generates 3.3V for VDDIO/VDDA/VDDD_3v3. The 5V Buck stops regulating after VBAT drops below 5V.
This is a very common automotive test so there must be a recommended solution to this. I'm looking for something that does not require additional circuitry if possible. I've tested holding the PHY in reset during this VBAT event and it operates as expected (INH stays high) so I believe a voltage supervisor/reset IC with a threshold around 6V would work, but I'm hoping there is a lower cost solution.
Hi,
Hi,
it would be great to have a schematic and scope plots with all supplies (VBAT, VDDA(3V3), VDDD(3V3), VDDD(1V8) or VDD(IO)) and INH.
Could be a device entered Power off mode. The TJA1101B continuously monitors the status of the supply voltages, this cannot be disabled. Once a supply voltage drops below the specified minimum operating threshold, the TJA1101B enters the fail-silent Standby mode and communication is halted. If an undervoltage is detected on VBAT, the TJA1101B switches to Power-off mode. After a transition from Power-off to Standby mode, undervoltage detection timeout is enabled once all supply voltages are available. When an undervoltage is detected, the TJA1101B switches to Sleep mode after tto(uvd).
The only valid SMI operations in Sleep mode are reading the POWER_MODE status bits in the Extended control register and issuing a Standby mode command (POWER_MODE = 1100).
BR, Petr