SAI BCLK configuration clarification

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SAI BCLK configuration clarification

431 次查看
Vignesh_tess94
Contributor I

I am using IMXRT1170 EVKB Board.  In SAI Configuration getting BCLK as 32fs . our project requirement is BCLK as 64 . what is the solution and configuration settings for this

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362 次查看
Vignesh_tess94
Contributor I

We tried the above solution which does not work .

Our project uses a Audio amplifier in DSP mode  which supports only 16/24 bit width, 2 channel for I2S and Fsync as 44khz or 48khz . but need BCLK as 64 Fsync. so we are not able to accomplish 64 with only 2 channel and 16bit width. is there any other setting to make  BCLK as 64 with above 16bit width and 2 channel?

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

You will need to mannualy modify TCR2 register. The bit clock is calculated by dividing the source clock for the bclk so you need to choose a clock source frequency so after the division the result is 64Fs.

Best regards,
Omar

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Bit clock is calculated as the result of the product of sample rate, bit width and channels so to increase the bit clock these variables need to be changed.
The product between bit width and channels must be 64 to accomplish the bclk = 64fs.
This can be done with SAI_TxSetBitClockRate() function.

Best regards,
Omar

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