Power Quicc II Pro performance problem

[yev15]

Hello,

In the last days, I had discovered performance problem in a new product based on MPC8323 Power Quicc processor.

The CPU is configured as following:

    External clock frequency 66MHz

    CSB clock frequency 133MHz

    DDR2 clock frequency 133MHz

    Quicc Engine clock frequency 200MHz

    Core clock frequency 333MHz

    Instruction cache enabled

    Data cache disabled

I've prepared and run 3 different test, used for performance monitoring:

    1 - loop of instructions that use internal registers only

    2 - loop of instructions that access internal memory (multi-user RAM)

    3 - loop of instructions that access external DDR2 memory

Results of these tests are listed below:

    Test 1 - 332.7 MIPS (mega-instructions per second) - as expected

    Test 2 - 12.8 MIPS when access to internal MURAM required - very low!!!

    Test 3 - 14.8 MIPS when access to external memory required - very low!!!

The CPU performance seems to be very low when access to internal/external RAM is required. It looks to me like a problem with Coherent System Bus arbitration, so I've reconfigured the Bus Arbiter to provide highest priority Core access to CSB:

    Arbiter Configuration Register (ACR) set to 0x00030000 - REPEAT disabled, Core is a park master, PIPE DEPH set to 4.

    System Priority Register (SPCR) set to 0x00700000 - Core CSB requests priority set to highest (3) level.

    Serial DMA Mode Register (SDMR) set to 0x800A0000 - emergency priority disabled, the QE always requests CSB with lowest priority.

The configuration shown above insures that Core gets highest CSB priority while other components (QE and PCI) gets lowest priority. That means that Core gets about 94% of the CSB time. But I see that it doesn't improves CPU efficiency when access to MURAM and external memory is required.

Does anybody have an idea that is the problem here?

Thanks,

Yevgeny

[bbaer]

Hi,

I'm using the MPC8349 rev.3 in very similar configuration.

External clock frequency 66MHz

    CSB clock frequency 133MHz

    DDR2 clock frequency 133MHz

    Quicc Engine clock frequency 266MHz

    Core clock frequency 400MHz

    Instruction cache enabled

    Data cache disabled

Peformance of write operation to DDR2 interface deteriorating by 80% after ECC enable. Try to close ECC and run your tests again. I have no idea why this is happening. Read operation performance has been reduced by 10% only (as expected) after ECC enable.

Boris

[yev15]

OK, I've got the explanation:

The DDR controller supports (only) four-beat burst access to DDR (four beats of double word = 32byte = cache line size). For single-beat reads, the DDR controller also performs four-beat burst read, but ignores the last three beats. It means, what with data cache disabled, the actual throughput to DDR is eight times lower.

Yevgeny