Max holdtime violation in FS mode while in master ACK

[mpattaje]

Hi,

As per NXP I2C specs UM10204 Rev 6, 4 Apr 2014, page 48, note 4, the maximum hold time for SDA driven by slave should not cross 900ns. 

In my simulation, this violation happens at the time of last bit of a byte of the slave device, later master device will send ACK. This is the place where SDA line must be released by slave device so that master device can drive ACK. What is the meaning of hold time violation here? Why that must apply when the line is released by slave? Why do you expect the slave to change the value here?  

-mpattaje

[mpattaje]

Hi Jozef,

As I pointed earlier, this is not about simulation, tool, company, or device. It is just about the I2C specs. My question is why should hold time apply when SDA is released by one device when ACK is expected. Doesn't the spec owner/creator, which is Phillips/NXP clarify this doubt? I clearly explained the condition. After last bit of the byte is sent by I2C slave, it will release the SDA bus. At that point why should hold time violation apply? Doesn't the specs need to clarify this?

-mpattaje

[JozefKozon]

Hi Muralikrishna Pattaje,

please state the part number of our component you are referring to.

With Best Regards,

Jozef

[mpattaje]

Hi Jozef,

No part number I know. I am simulating a design with Synopsys I2c Master VIP. It has this protocol violation error in my simulation. So I wanted to check how this hold violation is applicable when master is sending an ACK. 

-Murali

[JozefKozon]

Hi Muralikrishna Pattaje,

unfortunately I don't know the Synopsys products. I am not able to help you with their products. We support NXP components. I would recommend you to contact Synopsys support for help.

With Best Regards,

Jozef

[mpattaje]

Hi Jozef,

The question is not about Synopsys. It is about the I2C specs. I have mentioned the page of the specs also. The question is on the meaning of the hold time violation specs is referring. 

-mpattaje

[JozefKozon]

Hi Muralikrishna Pattaje,

please refer to the section 3.1.6 in the UM10204. The ninth bit is defined as acknowledge bit if the SDA is pulled low by the receiver during the SCL ninth bit. According to your picture, the SDA is held high, which defines the ninth bit as a Not Acknowledge signal. The tVD;ACK 900ns time is valid for ACK bit. So there is no violation, but the message transfer wasn't successful.

With Best Regards,

Jozef

[JozefKozon]

Hi Muralikrishna Pattaje,

there could be many reasons why the of hold time violation specifications. For example large bus capacitance, faulty component, wrong pull-up resistor values etc. Because you are using a simulation, non of these are possible. We would need to know the simulation tool and conditions, to reproduce the fault and then we would be able to answer you why the violation happens. Unfortunately we do not know either, so we cannot support you in this case.

I apologize for inconvenience.

With Best Regards,

Jozef