Hi,
The ORx/BRx and LAWx settings for my MPC8347 local bus peripherals are as follows:
BootRom Flash (GPCM):
OR0: 0xFF00_0FF4
BR0: 0xFF00_1001
4 MB DPRAM Chip #1 (UPMA):
OR1: 0xFFC0_1000
BR1: 0x3000_1881
Unused LCS (nLCS[2] (AP25) pulled high):
OR2: 0x0000_0000
BR2: 0x0000_0000
4 MB DPRAM Chip #2 (UPMB):
OR3: 0xFFC0_1000
BR3: 0x3040_18A1
For IMMR Space (note that I move IMMR very early in bootcode from 0xFF40_0000 to 0xFD00_0000 to avoid overlap with bootrom NOR flash on LCS0). And yes, I am following the recipe on how to move the IMMR as wrtten in the EARM UM (and the EARM UM Errata for page 5-6):
LBLAWBAR0: 0xFD00_0000
LBLAWAR0: 0x8000_0013
For bootrom flash (NOR) on LCS0:
LBLAWBAR1: 0xFF00_0000
LBLAWAR1: 0x8000_0017
For DPRAM chip #1 on LCS1:
LBLAWBAR2: 0x3000_0000
LBLAWAR2: 0x8000_0015
For DPRAM chip #2 on LCS3:
LBLAWBAR3: 0x3040_0000
LBLAWAR3: 0x8000_0015
As for the caching/MMU, I eventually use both (i.e. to I+D cache to copy executable faster out of flash to DDR, RTOS enables the MMU and caches formally during RTOS boot). However, if I set a HW breakpoint early in my bootcode with my JTAG ICE, before the RTOS even starts to boot and before I enable the cache (i.e. all MMU registers are 0x0000_0000 except for hash2 which is 0x0000_FFC0) but after I've configured all my LCSs, UPM machines and LAWs, I see the data mirroring problem on my two DPRAM chips by poking/peeking with my JTAG ICE.
Any clues as to what could be causing this problem so early in the boot-up process would be greatly appreciated? Please note that I always boot with an HRESET.
Victor.