LS1043A RGMII MAC TO MAC 1000M no phy no autonegogiation Output EC1_GTX_CLK is scale to 25 MHZ

[bahi]

From Linux (busybox) I'm trying to connect MAC3 of ls1043a. My configuration is: transmission: RGMII MAC to MAC there is no phy and no autonegociation clock input ECn_GTX_CLK125 are ok: input signals frequency is 125 MHz. my output signals ECn_GTX_CLK are ko: the output signals frequency is 25 MHz. So i'm not able to transmit to 1000Mbits. When the board is staring, the output frequency EC1_GTX_CLK and EC2_CTX_CLK signal with a frequency of 25 MHZ. Needed is 125 MHz. My question: what is the way to set the outputs EC1_GTX_CLK and EC2_GTX_CLK to 125 MHz. This is done by software from uboot or linux driver ? This is done by configuration from dts (ls1043a-ardb.dts, ls1043a-ardb.dtsi) How can i be sure thar there is no phy and no autonegociation ? This is checked from dts ? Thanks for your help

[yipingwang · Accepted solution]

Please refer to the following update from the AE team.

I did a presentation for Fiberhome a while back. Look at slide #37. What is your IF_MODE?

For RGMII, the TX is source synchronous (we send the clk with the data).. The speed selection in the MAC will control the dividers to give the correct freq on TX.

For RX, you have to supply the correct freq to the rx clk (2.5MHz, 25MHz, or 125HMz).

[bahi]

Hi Yiping,

thank your for help. The document is very useful.

IF_MODE register content is 0x600a0000

bit 0-bit 15 = 0x0000

bit 16 = 0 => ena
bit 17 = 1 => ssp
bit 18 = 0 => ssp
bit 19 = 1

bit 20 = 0
bit 21 = 0
bit 22 = 0
bit 23 = 0

bit 24 = 0
bit 25 = 0
bit 26 = 0
bit 27 = 0

bit 28 = 0
bit 29 = 1 => rg
bit 30 = 1 => if_mode
bit 31 = 0 => if_mode

Best regards

Brahim

[bahi]

Hi Yiping,

from the document LS1043ADPAARM 6.4.3.3.1 Interface Mode Register (IF_MODE) table 6-87. IF_MODE Field Description I read:

17–18 SSP
• 00 - 100 Mbps RGMII (valid only if ENA=0)
• 01 - 10 Mbps RGMII (valid only if ENA=0)
• 10 - 1 Gbps RGMII (valid only if ENA=0)
• 11 - Reserved

for 1Gbps bit 17 = 1 and bit 18 = 0 or is it the contrary ?
I'm not sure of the higher significant bit in the table.

30–31 IFMODE
• 00 - 10G interface mode
• 01 - MII mode
• 10 - GMII mode (also for RGMII)
• 11 - Reserved

for GMII mode (also RGMII) bit 30 = 1 and bit 31 = 0 or is it the contrary ?
I'm not sure of the higher significant bit in the table.

Best regards

Bahi

[bahi]

The interface with if_mode register is big endian. So I swapped the bit0-15 with the bit16-31 and now the frequency is OK (EC1_GTX_CLK output is 125 MHz):

bit 31-bit 16 = 0x0000

bit 15 = 0 => ena
bit 14 = 1 => ssp
bit 13 = 0 => ssp
bit 12 = 1

bit 11 = 0
bit 10 = 0
bit 9 = 0
bit 8 = 0

bit 7 = 0
bit 6 = 0
bit 5 = 0
bit 4 = 0

bit 3 = 0
bit 2 = 1 => rg
bit 1 = 1 => if_mode
bit 0 = 0 => if_mode

u32 value is 0x00005006

Thank you for your help.
Best regards
Bahi