I have made my own circuit but the problem is that on there is half power difference between my simulation results and my layout results. This is why I am trying to understand the test circuit so that it can help me debug my own design. However, I can not really understand the matching network technique used in the test circuit. The data sheet is attached. The circuit being mentioned is on page 10.
Solved! Go to Solution.
> Input impedance matching.
Quater wave transmission line impedance transformer can match zin to 50 Ohm. However, the same PCB layout is used for 2500-2700 and 2300-2400 MHz frequency bands. In the D53817 design, impedance of the wide TL is set greater than the optimal impedance and the length is shorter. C2 capacitor is used to eliminate mismatch of non-optimal trace line impedance transformer. Changing the value and position of the capacitor provides tuning capability for the circuit.
Copper Patches next to signal traces can be used as attachment points for wire or solder to create tuning C or L. If not connected, they do not affect the functionality.
> Output DC bias.
C4, C8 decoupling capacitors are placed at quater wave length distance from the output pad. This network has high impedance at the RF frequency 2350MHz. However, at low frequencies the bias nework is inductive and together with output capacitance of the transistor it may cause low frequency resonances. This resonance will modulate drain voltage and will limit the video bandwidth of the amplifier. Two DC bias networks are provided to reduce inductance of the of bias and so to move resonance frequency up by 1.4 times.
C12,C11,C9,C10,C13 low frequency DC feed capacitors.
> Output impedance matching.
It is quater wave trace line transformer. C3 (C14) capacitor tunes the circuit fo required frequency band.
Have a great day,
Pavel
NXP TIC
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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> Input impedance matching.
Quater wave transmission line impedance transformer can match zin to 50 Ohm. However, the same PCB layout is used for 2500-2700 and 2300-2400 MHz frequency bands. In the D53817 design, impedance of the wide TL is set greater than the optimal impedance and the length is shorter. C2 capacitor is used to eliminate mismatch of non-optimal trace line impedance transformer. Changing the value and position of the capacitor provides tuning capability for the circuit.
Copper Patches next to signal traces can be used as attachment points for wire or solder to create tuning C or L. If not connected, they do not affect the functionality.
> Output DC bias.
C4, C8 decoupling capacitors are placed at quater wave length distance from the output pad. This network has high impedance at the RF frequency 2350MHz. However, at low frequencies the bias nework is inductive and together with output capacitance of the transistor it may cause low frequency resonances. This resonance will modulate drain voltage and will limit the video bandwidth of the amplifier. Two DC bias networks are provided to reduce inductance of the of bias and so to move resonance frequency up by 1.4 times.
C12,C11,C9,C10,C13 low frequency DC feed capacitors.
> Output impedance matching.
It is quater wave trace line transformer. C3 (C14) capacitor tunes the circuit fo required frequency band.
Have a great day,
Pavel
NXP TIC
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi Pavel,
I am new in designing an LDMOS RF amplifier circuut. So, my question is, according to the LDMOS's datasheet, what do you do exactly to tune the device's Zin (not Zsource) impedance according to the load pull efficiency tuned table? Is it by tuning the lenght of the wide traces (low Z trace) at each gate and drain terminals?