Daniel,
Thanks for the response.
I know the USB TAP and flash_over_jtag dongles have hardware reset lines, so I assume they halt and then reset the core to clear the OCCS registers and flash divisor. Then, the system clock is in a known state and it is okay to use a constant flash divisor, correct?
I am trying to impliment a JTAG flash programmer from an embedded 8051 processor. My primary issue at the moment, is that once a part is erased and then power cycled, I cannot get the chip to go into debug mode reliably. The JTAG debug instructions return 0x01 "Normal/Reset mode" instead of the 0x0D "Debug mode" I was asking about the divisor because I'm trying to reconcile some details and get to the bottom of my problem.
I followed "AN1973 - Production Flash Programming for 56F8300.pdf" which referenced the "AN1935. - Programming On-Chip Flash Memories of 56f80x devices using the JTAG.pdf" Unfortunatly I found out half way through the developement that there were some significant differences between the OnCE and EOnCE debuggers and I have been trying to work from the flash_over_jtag_v2 source code.
If you know anything about accessing the EOnCE module I would appreciate some guidance.
Thanks,
-Jim