A2I20H060NR1 gate biasing

[docha]

dear,

I would like to use a 1k potentiometer between regulated +5V and GND, to supply each VGG' with 2.2k in serial.

Is it a good choice for -30 to +85 deg design?

Where can we find eval board documents?

Best regards

A2I20H060GNR1

A2I20H020GNR1

A2I20H060NR1

A2I20H020NR1

[docha]

Dear,

we have run our board with A2I20H060GNR1 (bent pins). Driver is MMG20024HT1. Layout is similar to eval board (straight pins).
  We would like to know the recommended process to adjust bias settings.

For carrier amplifier, we use Idq1=24mA, Idq2=149mA.
For peaking amplifier, we use Vgs1b=1.65V, Vgs2b=1.3V.

 With these settings we get a ~3dB 'bump' in the AM/AM response.

See attached, in blue curve Gain response vs input power, in black curve Output power vs input power.
Traces with markers are with recommended  bias, others with bias Vgs1b=1.87/Vgs2b=2.32V.



In front of PA we would like to use a lineariser chip, that would prefer to see 1dB max ripple in AM/AM response.

Thanks for your help.
Best regards.

[LPP · Accepted solution]

Your solution is quite applicable. 1k potentiometer between +5V and GND along with 2.2k resistor at VGSx pins will provide required offset at the target quiescent current level.

Please, you can request design files for test boards through  NXP support. We can't put this files at this forum.
Have a great day,
Pavel

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