Using : MBDToolbox 4.2.1,with hotfix for register access blocks.
Using: S32K144 LQFP-100, on proprietary hardware board
Setting the clock frequency to 80Mhz violates the data sheet frequency limits for the PLL.
Setting: MBD_S32K1xx_Config_Information: S32K144 / 80mhz clock, Xtal = 8Mhz External (see picture)
This generates a s32k_clock_init.c file for initializing the VCO/PLL. The relevant
#if XTAL_FREQ == 8000000
#define MBDT_PLLPREDIV SCG_SPLL_CLOCK_PREDIV_BY_1
#define MBDT_SOSCDIV SCG_ASYNC_CLOCK_DIV_BY_1
...
#if CORE_CLK_FREQ == 80000000
##define PLL_MULT 4U // mult = 2
#define POWER_MODE POWER_MANAGER_RUN
#define PLL_ASYNC_DIV2 SCG_ASYNC_CLOCK_DIV_BY_4
...
.spllConfig =
{
.initialize = true, /* Initialize */
/* SPLLCSR */
.monitorMode = SCG_SPLL_MONITOR_DISABLE,/* SPLLCM */
.locked = false, /* LK */
/* SPLLCFG */
.prediv = MBDT_PLLPREDIV, /* PREDIV */
.mult = PLL_MULT, /* MULT */
.src=0U, /* SOURCE */
/* SPLLDIV */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1,/* SPLLDIV1 */
.div2 = PLL_ASYNC_DIV2, /* SPLLDIV2 */
},
This configuration takes the 8Mhz SOSC input, divides it by one, and multiplies it by 20 to generate an SPLL_VCO output frequency of 160Mhz.
The problem is that section 6.2.5 of the data sheet, SPLL electrical specifications, requires the FVCO_CLK of the PLL to be between 180Mhz and 320Mhz.
While the misconfiguration has not resulted in any obvious problems on the bench, it the hardware designers thought that 160mhz was usable in all process / temperature / voltage variations, they would have listed 160mhz as the minimum PLL output frequency.
In-spec 80Mhz operation requires the SPLL_VCO to use /1 and *40, and the DIVCORE should be set to /2.
