Hello Martin,
Thank you for your reply. That was very helpul. I used 0xA0000000 as the base address and that works well on the TWR-MEM.
So, I try to implement the same concept on a customized board with a 16bit SRAM. The figure below shows our hardware schematic.
The memory is word-addressable (16-bit), so the FlexBus word address line FB_AD[1] is connected to A[0] of the memory.
Thus, FB_A[15:1] are connected to A[14:0] of the memory.
I initialize the flex bus in 16bit mode using the following code:
#define FLEX_BASE_ADDRESS 0xA0000000
SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; // Enable the clock to the FlexBus
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x0); //FlexBus Clock not divided
// Set the GPIO ports clocks
SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
// Set the GPIO ports clocks
SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
/*address bus*/
PORTB_PCR18 = PORT_PCR_MUX(5); // fb_ad[15]
PORTC_PCR0 = PORT_PCR_MUX(5); // fb_ad[14]
PORTC_PCR1 = PORT_PCR_MUX(5); // fb_ad[13]
PORTC_PCR2 = PORT_PCR_MUX(5); // fb_ad[12]
PORTC_PCR4 = PORT_PCR_MUX(5); // fb_ad[11]
PORTC_PCR5 = PORT_PCR_MUX(5); // fb_ad[10]
PORTC_PCR6 = PORT_PCR_MUX(5); // fb_ad[9]
PORTC_PCR7 = PORT_PCR_MUX(5); // fb_ad[8]
PORTC_PCR8 = PORT_PCR_MUX(5); // fb_ad[7]
PORTC_PCR9 = PORT_PCR_MUX(5); // fb_ad[6]
PORTC_PCR10 = PORT_PCR_MUX(5); // fb_ad[5]
PORTD_PCR2 = PORT_PCR_MUX(5); // fb_ad[4]
PORTD_PCR3 = PORT_PCR_MUX(5); // fb_ad[3]
PORTD_PCR4 = PORT_PCR_MUX(5); // fb_ad[2]
PORTD_PCR5 = PORT_PCR_MUX(5); // fb_ad[1]
PORTD_PCR6 = PORT_PCR_MUX(5); // fb_ad[0]
/*data bus*/
PORTB_PCR20 = PORT_PCR_MUX(5); // fb_ad[31] used as d[15]
PORTB_PCR21 = PORT_PCR_MUX(5); // fb_ad[30] used as d[14]
PORTB_PCR22 = PORT_PCR_MUX(5); // fb_ad[29] used as d[13]
PORTB_PCR23 = PORT_PCR_MUX(5); // fb_ad[28] used as d[12]
PORTC_PCR12 = PORT_PCR_MUX(5); // fb_ad[27] used as d[11]
PORTC_PCR13 = PORT_PCR_MUX(5); // fb_ad[26] used as d[10]
PORTC_PCR14 = PORT_PCR_MUX(5); // fb_ad[25] used as d[9]
PORTC_PCR15 = PORT_PCR_MUX(5); // fb_ad[24] used as d[8]
PORTB_PCR6 = PORT_PCR_MUX(5); // fb_ad[23] used as d[7]
PORTB_PCR7 = PORT_PCR_MUX(5); // fb_ad[22] used as d[6]
PORTB_PCR8 = PORT_PCR_MUX(5); // fb_ad[21] used as d[5]
PORTB_PCR9 = PORT_PCR_MUX(5); // fb_ad[20] used as d[4]
PORTB_PCR10 = PORT_PCR_MUX(5); // fb_ad[19] used as d[3]
PORTB_PCR11 = PORT_PCR_MUX(5); // fb_ad[18] used as d[2]
PORTB_PCR16 = PORT_PCR_MUX(5); // fb_ad[17] used as d[1]
PORTB_PCR17 = PORT_PCR_MUX(5); // fb_ad[16] used as d[0]
PORTB_PCR19 = PORT_PCR_MUX(5); // fb_oe_b
PORTC_PCR11 = PORT_PCR_MUX(5); // fb_rw_b
PORTD_PCR1 = PORT_PCR_MUX(5); // fb_cs0_b
PORTD_PCR0 = PORT_PCR_MUX(5); // fb_ale
FB_CSAR0 = (unsigned int)&MRAM_START_ADDRESS_8; //Set Base address
FB_CSCR0 = FB_CSCR_PS(2) // 16-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_WS(0x2) // 2 wait states
;
FB_CSMR0 = FB_CSMR_BAM(0x7) //Set base address mask for 512K address space
| FB_CSMR_V_MASK //Enable cs valid signal
;
I try to write and read a 16bit value to the SRAM over flexbus by using the following code:
int wdata16 = 1;
unsigned short *p_16;
p_16 = (unsigned short*) FLEX_BASE_ADDRESS;
for(n=0x00010;n<0x001F;n++) //address offset
{
*(p_16 + n) = wdata16;
rdata16 = *(p_16 + n);
wdata16<<=1;
}
the problem is that rdata value is different from wdata! I'm not sure if I missed something in hardware or firmware side!
any comment on this issue kindly appreciated.
Cheer!
