Crash with IRQ7 and MQX 4.0

[cedricpalabost]

Hello,

I'm using MQX 4.0 with a 52259EVB board and I have a crash with my application...

I create a new project based on the example GPIO. Then, I modify the source code to activate IRQ on the IRQ7 pin like this :

lwgpio_init(&btn1, GPIO_PORT_NQ | GPIO_PIN7, LWGPIO_DIR_INPUT, LWGPIO_VALUE_NOCHANGE)

Code of the interrupt routine :

void int_service_routine(void *pin)

{

    lwgpio_int_clear_flag((LWGPIO_STRUCT_PTR) pin);

    ul_CompteurIT++;

}

In the main loop, the counter ul_CompteurIT is displayed each second (I have 50 interrupts per second).

This program crashes after some seconds and goes to a "dummyfn1".

I try another solution :

I declare a new interrupt routine like this :

__declspec(interrupt) void SecteurSync_Interrupt(void)

{

MCF_EPORT_EPFR = 0x80;

ul_CompteurIT++;

}

and use : _int_install_kernel_isr(lwgpio_int_get_vector(&btn1), SecteurSync_Interrupt);

It's work well !

An ISR doesn't work, an KERNEL ISR works !

any ideas?

Thanks in advanced for your help.

[cedricpalabost]

Hi Martin,

Thanks for your help and your quick answer.

OK I understand, I will manage it with kernel isr. But I have another question :

Must I disable this interrupt in some cases ? For example when I write data in flash (by using FLASHX functions) ?

This interrupt is not maskable and could disturb MQX during some traitment.

Best regards,

Cedric.

[Martin_]

Hi Cedric,

Without digging into details about flashx on ColdFire and ColdFire internal flash, I would say yes. Typically you need to disable accesses (instruction fetches or data load) to flash array during execution of flash programming algorithm. Alternatively, if that kernel_isr is kind of critical, perhaps you can relocate the code to internal SRAM and execute it from there, then you won't need to disable this interrupt. (as IRQ7 is non-maskable, you can't use the SR register, the interrupt would need to be disabled in the peripheral module).

Martin

[cedricpalabost]

Hi Martin,

Thank you very much for your help.

BR,

Cédric.

[Martin_ · Accepted solution]

If I remember correctly, IRQ pin interrups on ColdFire have fixed priority. For IRQ 7 that would be priority 7, which is the non-maskable interrupt level to ColdFire core. Therefore it must be handled by application as such (= in MQX install kernel isr for it and this routine must not call MQX API).