eTPU2 AN4907SW verify gap keeps failing

[Jason_AE]

Hi all,

When supplying the eTPU with a 60-2 crank signal, the crank state becomes FS_ETPU_CRANK_VERIFY_GAP quite often but not at the gap so the eTPU (often) fails to get full sync. When the crank_state goes to 6, a digital output of the microcontroller is pulled low for 10ms. In the figure of the measurement below the blue line is the digital output and the red line is the crank signal (as measured on the microcontroller pin)

Multiple settings have been tried for the ratio's but the measurement has been done with the settings below:
gap_ratio 0.33
win_ratio_normal 0.8
win_ratio_across_gap 0.2
win_ratio_after_gap 0.45
win_ratio_after_timeout 0.8

For completeness the same signal has been tested on both channel 1 as channel 2 with the same results. Even when the gap_ratio was set to 0.1 the crank state still became crank_verify_gap, which I think it really shouldn't anymore. As far as I understand the crank_state will become crank_verify_gap when the AB part of the ABA test has been passed.

I feel like I am missing something obvious but after days of looking I still haven't found it, hopefully someone here could point me in the right direction.

Many thanks in advance,

Jason

[davidtosenovjan · Accepted solution]

1) Isn’t eTPU DATA RAM being overwritten somehow?

2) Is your configuration meaningful? (You may provide etpu_gct.c/.h files)

3) To understand what happens we would need more information. But don't specify which signals/variables to record. Minimum 1) inj_states, 2) eTPU DATA RAM starting from inj_instance.cpba - in normal state, after error, ….

[Jason_AE]

Sorry for the late respons, while trying to figure out how to get 'eTPU DATA RAM starting from inj_instance.cpba' I found out that the RAM indeed wasn't correct.

Thank you for your reply, this really helped!