We had port freeRTOS v8.2.3 to MPC5746C, but when I porting the EEPROM emulation driver, I found that need to disable the D-Cache (define the macro "DCACHE_AVAILABLE" ) when exec "FSL_WriteEeprom" and "FSL_MainFunction", If not define the DCACHE_AVAILABLE macro, the swapping will failure, But after I disable the D-Cache, the freeRTOS may run unsteadiness or trig Machine Check Exception.
(Similar to this post Disable Dcache of 5744 will make CCP unsteadiness )
Finally, I set the EEPROM area (0xF90000 ~ 0x00F9FFFF) "cache inhibit" in the SMPU, and undefine the macro "DCACHE_AVAILABLE", then both the EEE Driver and freeRTOS work fine.
By the way, I create a test task to R/W the EEE,after 10K cycle, it still works fine:
for( ;; )
{
#if DRV_DEBUG_ENABLE_SWT == 1
drv_cpu_feeddog();
#endif
/* Not very exiting - just delay... */
vTaskDelay( 25 );
drv_eee_readData(0x66,24,TmpBuf2);
LOG("R1:%3d\r\n",TmpBuf2[0]);
TmpBuf2[0] += 1;
drv_eee_writeData(0x77,24,TmpBuf2);
/* delay */
vTaskDelay( 25 );
drv_eee_readData(0x77,24,TmpBuf1);
LOG("R2:%3d\r\n",TmpBuf1[0]);
TmpBuf1[0] += 1;
drv_eee_writeData(0x66,24,TmpBuf1);
}