[MPC5777M] FEC frame reception

[eschick]

Hi all,

I've been sitting on this problem for a while now. I have an MPC5777M device here, on which I would like to establish a simple ethernet communication. For that purpose I use the FEC application for the MPC564xB/C, as the FEC is the same on that device. My board is connected to my computer via an USB-2-Ethernet converter and I catch the Ethernet frames with wireshark. I configure the FEC according to the application note and similar to the example project that is linked together with the appnote(AN4577SW). I'm sending simple ARP requests to my computer and they are properly recognised and also responded by the computer. However the problem is that I do not receive the response.

First I was thinking that there is something wrong with the interrupt configuration, because no RX interrupt was generated, bun if I skip the PHY configuration and enable the internal loopback, the RX interrupt is generated and I receive my transmitted frame. Another idea was that the frame could be droped because of the destination address recognition, but the frame is send to my configured MAC address (FEC.PALR and FEC.PAUR) and FEC.RCR.PROM Bit (for accepting all frames) is also set.

Has anyone an idea what could cause this issue?

Regards,

Efim

[PetrS]

Hi Efim,

It could be wrong pad setting.

Can you share your FEC IO configuration and schematic of MCU to PHY connection if you are using your own designed board?

BR, Petr

[eschick]

Hi Petr,

I'm using the MPC57xx Motherboard (MPC57XXMB_RevB) together with the MPC5777M_416DS Daughter Card (MPC5777M-416DS). I configure the pads as follows:

    SIUL2.MSCR_IO[34].R = 0x31090003;    /* Set to FEC_MDIO     */
    SIUL2.MSCR_IO[924].R = 0x40080001;    //MDIO input pad
    SIUL2.MSCR_IO[35].R = 0x22000001;        /* Set to FEC_MDC     must be strong drive for MDIO & MDC */
    SIUL2.MSCR_IO[46].R = 0x32000001;    /* Set to FEC_TX_EN  */
    SIUL2.MSCR_IO[47].R = 0x32000001;    /* Set to FEC_TXD[0] */
    SIUL2.MSCR_IO[76].R = 0x32000001;    /* Set to FEC_TXD[1] */
    SIUL2.MSCR_IO[196].R = 0x32000001;    /* Set to FEC_TXD[2] */
    SIUL2.MSCR_IO[197].R = 0x32000001;    /* Set to FEC_TXD[3] */
    SIUL2.MSCR_IO[931].R = 0x40080001;     /* Set to FEC_COL     */
    SIUL2.MSCR_IO[926].R = 0x40080001;     /* Set to FEC_CRS     */
    SIUL2.MSCR_IO[923].R = 0x40080001;    /* Set to FEC_RX_CLK */
    SIUL2.MSCR_IO[925].R = 0x40080002;     /* Set to FEC_RX_DV  */
    SIUL2.MSCR_IO[927].R = 0x40080001;     /* Set to FEC_RXD[0] */
    SIUL2.MSCR_IO[928].R = 0x40080001;     /* Set to FEC_RXD[1] */
    SIUL2.MSCR_IO[929].R = 0x40080001;     /* Set to FEC_RXD[2] */
    SIUL2.MSCR_IO[930].R = 0x40080001;     /* Set to FEC_RXD[3] */
    SIUL2.MSCR_IO[932].R = 0x40080001;     /* Set to FEC_RX_ER  */
    SIUL2.MSCR_IO[922].R = 0x40080003;        /* FEC_RXDCLK input PM[6] - take from PC[10]*/

Regards,

Efim

[PetrS · Accepted solution]

Hi Efim,

try to use below config. Also remove J18 jumper on motherboard and connect J18.2 to P20.9. This connects PHY's RX_CLK to PM[8]/MCU's RXCLK input.

void InitEthernetSIU(void)
{
    #define MSCR_TO_IMCR_OFFSET 512
    
    SIUL2.MSCR_IO[47].R = 0x22300001;    // PC[15], Set to FEC_TXD0
    SIUL2.MSCR_IO[76].R = 0x22300001;    // PE[12], Set to FEC_TXD1
    SIUL2.MSCR_IO[196].R = 0x22300001;    // PM[4], Set to FEC_TXD2
    SIUL2.MSCR_IO[197].R = 0x22300001;    // PM[5], Set to FEC_TXD3

    SIUL2.MSCR_IO[46].R = 0x22300001;    // PC[14], Set to FEC_TXEN

    SIUL2.MSCR_IO[198].R = 0x22300001;    // PM[6], Set to FEC_TX_ER, not connected to PHY
    
    SIUL2.MSCR_IO[174].R = 0x00080000;    // PK[14], Set to FEC_TX_CLK
    SIUL2.MSCR_MUX[923-MSCR_TO_IMCR_OFFSET].B.SSS = 2;    // 923-512

    SIUL2.MSCR_IO[44].R = 0x00080000;    // PC[12], Set to FEC_RXD0
    SIUL2.MSCR_MUX[927-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[45].R = 0x00080000;    // PC[13], Set to FEC_RXD1
    SIUL2.MSCR_MUX[928-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[193].R = 0x00080000;    // PM[1], Set to FEC_RXD2
    SIUL2.MSCR_MUX[929-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[175].R = 0x00080000;    // PK[15], Set to FEC_RXD3
    SIUL2.MSCR_MUX[930-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[192].R = 0x00080000;    // PM[0], Set to FEC_RXDV
    SIUL2.MSCR_MUX[925-MSCR_TO_IMCR_OFFSET].B.SSS = 2;

    SIUL2.MSCR_IO[195].R = 0x00080000;    // PM[3], Set to FEC_RXER
    SIUL2.MSCR_MUX[932-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[194].R = 0x00080000;    // PM[2], Set to FEC_COL
    SIUL2.MSCR_MUX[931-MSCR_TO_IMCR_OFFSET].B.SSS = 1;

    SIUL2.MSCR_IO[43].R = 0x00080000;    // PC[11], Set to FEC_CRS
    SIUL2.MSCR_MUX[926-MSCR_TO_IMCR_OFFSET].B.SSS = 1;    // 926-512

    SIUL2.MSCR_IO[200].R = 0x00080000;    // PM[8], Set to FEC_RX_CLK
    SIUL2.MSCR_MUX[922-MSCR_TO_IMCR_OFFSET].B.SSS = 2;

    SIUL2.MSCR_IO[35].R = 0x22300001;    // PC[3], Set to FEC_MDC

    SIUL2.MSCR_IO[34].R = 0x21380003;    // PC[2], Set to FEC_MDIO
    SIUL2.MSCR_MUX[924-MSCR_TO_IMCR_OFFSET].B.SSS = 1;    // 924-512
 
}

BR, Petr

[eschick]

Hi Petr,

thank you, your configuration really solves my issue. Now I'm able to receive frames and the RX Interrupt is generated properly. But could you please tell me what is the exact difference between your and my configuration? And why do you use another RX_CLK input pin?

Best regards,

Efim

[PetrS]

You have wrong setting for input signals. Pads are configured by MSRC registers, which is array of 1024 registers.

In most cases this array is splitted into two within header files with indexes 0-512, first MSCR followed by IMCR (have offset 512). MPC5777M header uses MSCR_IO and MSCR_MUX instead of MSCR and IMCR.

For inputs the IBE bit of respective MSCR_IO register have to be set. Moreover SSS bits of MSCR_MUX register have to be set accordingly.

Then considering pad PM[8], as per table below, the necessary setting for FEC_RXCLK function will be

SIUL2.MSCR_IO[200].R = 0x00080000;    // PM[8], Set to FEC_RX_CLK

SIUL2.MSCR_MUX[922-512].B.SSS = 2;

 

The FEC_RXCLK can be selected on PM[6] or PM[8]. I used PM[8].

BR, Petr

[eschick]

Thank you very much for the explanation. I didn't know that the MSCR is splitted within the header and I wonder why I didn't receive a compiler error in case of writing e.g. the MSCR_IO[922], since it is not declared in the header. Well, I will take care of it in the future.

Best regards,

Efim