MPC5777C; NCF 42 and sofware reset

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MPC5777C; NCF 42 and sofware reset

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krywes
Contributor I

Hello!

If I configure the FCCU to perform a reset when NCF 42 triggers (Lockstep/RCCU disable), will that then trigger
trigger a FCCU reset if I perform a software reset (SIU_SRCR[SSR] = 1)?

Currently we have this configuration, and when we perform the software reset the CPU will freeze much in the same
way as it does if we start debugging of Core1 with NCF42 reaction enabled. Disabling NCF 42 reaction will make
the software reset behave as expected, so it would be nice if someone could confirm that this is the case, or if
it is something else that causes the CPU to freeze.

Best regards
/Jimmy Westerlund

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I see.

You must clear NCF42 reaction before software reset. How I already said NCF[42] is always present after RESET. Also another point is that FCCU setup in not changed by software reset (RM Figure 50-1, Other Internal Reset).

Immediately after such reset NCF42 reset response is triggered what's should probably lead in reset escalation i.e. permanent reset at the end.

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krywes
Contributor I

Downloading is basically split into two parts. The first considers authentication of downloading tool etc which ends with the diagnostics server performing a software reset to hand over control to the bootloading mechanism. This initiates the second part which eventually ends up with code running from external RAM which performs the actual writing into internal flash memory.

The problem occurs during this reset, so the problem is not really associated with the actual software downloading. That was just the way we found the problem. If we issue a reset command from our CLI (which results in SIU_SRCR[SSR] being set) the same thing happen; both cores gets stuck and is held in reset until HW reset or POR.


The FCCU_CTRL[DEBUG] flag is disabled. Enabling it has no effect on how the CPU behaves during a software reset.

Best regards

/Jimmy W

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I am not sure if I understand your issue. I would recommend to see following example code, I recently shared:

https://community.nxp.com/docs/DOC-347166 

NCF[42] is always present after RESET (if lockstep is enabled in DCF record) and needs to be cleared after starting of the second core. Reset reason is not important for this behavior.

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krywes
Contributor I

Hi David.

Guess I need to explain my situation a little better. We are running both cores with lockstep enabled (no DCFs are used) and the FCCU has been setup to react on a set of NCF's (including NCF[42]). Software is running just fine until we attempt to perform a software download. As part of the download sequence the CPU will perform a software reset to hand over control to the bootloader which will perform the actual update.

Until recently, the NCF[42] was set up to not cause any FCCU reaction and download worked just fine. But in a recent update, NCF[42] was activated and setup to cause an immediate FCCU reset. This caused download sequence to fail and we found that when core1 performed the software reset, the CPU got stuck in reset (RSTOUT active). By temporarily disabling NCF[42] reaction prior to software download, the download sequence works, i.e. the CPU is reset and core 0 boots up as expected.

I compared this to what happen when I attach the CPU to a debugger and halt Core 1 while NCF[42] reaction is active. As debugging this will disable/halt RCCU this also trigger FCCU reaction with the same result as we noticed above, i.e. both cores gets stuck in reset and RSTOUT is active.

My suspicion was hence that maybe a software reset will have much the same effect. As a SW reset will not reset the FCCU and if NCF[42] is(/becomes) present after any reset (as you stated above), wouldn't that mean that the FCCU would kick in and perform a FCCU reset as a response to the SW reset?

If so I guess that would mean that if you intend to perform a software reset, you must first disable NCF42 reaction?

By the way, is the expected behaviour of halting Core1 using a debugger while NCF[42] is configured to peform a reset that the CPU will actually be held in reset, rather then "just" performing a FCCU reset and reboot the CPU?

Best Regards
/Jimmy W

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davidtosenovjan
NXP TechSupport
NXP TechSupport

How you are downloading new software? What is your setting FCCU_CTRL[DEBUG]?

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