MPC5775E eDMA channel 0 interrupt somehow disabled

[0xEC]

hi everyone,

I am using eDMA to fill CFIFO0 for eqADC from system memory to CFPR(Command fifo push register)

I set DMA request of related channel to create DMA request. When I start the eDMA channel it starts to transfer data from system memory to CFIFO, but after one time fill eDMA won't be triggered again. I debug it and saw that eDMA ERQ register's related bit is set to 0 somehow. Do you have any issue like this?

RM says that CFFEx, CFFSx and CFFFx bits must be set to request DMA.

this is my debug output which shows all three bits are set,

eDMA channel 0 enable request disabled after one transfer for CFIFO. Should I enable again manually each time the eDMA channel 0 finishes the transfer?

best,

[davidtosenovjan]

Pay attention to following example code:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5674F-eQADC-eDMA-Single-Scan-CW210/ta...

In the main file you may see how to properly set DMA TCD descriptors.

[davidtosenovjan · Accepted solution]

Apparently you have set DREQ bit, this needs to be set to zero.

[0xEC]

I tried this one also, from RM I read it, it is set in eDMA TCDx_CSR register. I disable it by EDMA_DRV_DisableRequestsOnTransferComplete(eqadc1_config0.cfifoConfigArray[0].dmaVirtualChan, false);
it behave same.