MPC5744P system clock config problem

[mkaradag1757]

Hi,

I am using DEVKIT-MPC5744P. I set clock configuration according to AN5393 clock calculator guide that refer to excel file. Clocks are set to max and system clock set to 200 MHz. When I calculate the sys clc via logic analyzer I observed that system clock is 10~20 MHz. I examined the code register level generated by calculator but I did not find any mistake. I shared clock init and init perip clock gen. below.

How can I set the sys clc(main clock) to 200 MHz. Can you help me at this point?

Thanks for your interesting.

//Enable XOSC, PLL0, PLL1, and enter RUN0 with PLL1_PHI as system clock (200 MHz).
void SysClk_Init(void)
{
MC_CGM.AC3_SC.R = 0x01000000; //Connect XOSC to the PLL0 input.
MC_CGM.AC4_SC.R = 0x03000000; //Connect PLL0_PHI1 to the PLL1 input.

//Set PLL0 to 160 MHz with 40 MHz XOSC reference.
PLLDIG.PLL0DV.R = 0x40024020; //PREDIV = 4, MFD = 32, RFDPHI = 2, RFDPHI1 = 8

MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,XOSCON,PLL0ON,syclk=IRC

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

//Set PLL1 to 200 MHz with 40 MHz PLL0_PHI1 input.
PLLDIG.PLL1DV.R = 0x00020014; //MFD = 20, RFDPHI = 2
PLLDIG.PLL1FD.R = 0x00000000; //EnableandconfigurationfractionalmultiplierforPLL1

MC_ME.RUN_PC[0].R = 0x000000FE; //Enable peripherals to run in all modes
MC_ME.RUN0_MC.R = 0x001300F4; // RUN0 cfg: IRCON, XOSCON, PLL0ON, PLL1ON, syclk=PLL1_PHI

MC_CGM.SC_DC0.R = 0x80090000; //Divide system clock by 10 to achieve PBRIDGEx_CLK of 20 MHz

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
}
void InitPeriClkGen(void)
{
MC_CGM.SC_DC0.R = 0x80090000; //PBRIDGEx_CLK at system clock divided by 10 (20 MHz).
MC_CGM.AC0_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 0.
MC_CGM.AC0_DC0.R = 0x800F0000; //MOTC_CLK: Enabled at Auxiliary Clock 0 divide by 16(10 MHz).
MC_CGM.AC0_DC1.R = 0x80070000; //SGEN_CLK: Enabled at Auxiliary Clock 0 divide by 8(20 MHz).
MC_CGM.AC0_DC2.R = 0x80010000; //ADC_CLK: Enabled at Auxiliary Clock 0 divide by 2(80 MHz).

/* Auxiliary Clock 1 is always sourced from PLL0_PHI. */
MC_CGM.AC1_DC0.R = 0x80010000; //FRAY_CLK: Enabled at Auxiliary Clock 1 divided by 2 (40 MHz).
MC_CGM.AC1_DC1.R = 0x80010000; //SENT_CLK: Enabled at Auxiliary Clock 1 divided by 2 (80 MHz).

/* Auxiliary Clock 2 is always sourced from PLL0_PHI. */
MC_CGM.AC2_DC0.R = 0x80010000; //CAN_CLK: Enabled at Auxiliary Clock 2 divided by 2 (40 MHz).

MC_CGM.AC5_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 5.
MC_CGM.AC5_DC0.R = 0x80070000; //LFAST_PLL: Enabled at Auxiliary Clock 5 divided by 8 (20 MHz).

MC_CGM.AC6_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 6.
MC_CGM.AC6_DC0.R = 0x80000000; //CLKOUT0: Enabled at Auxiliary Clock 6 divided by 1 (200 MHz).

MC_CGM.AC10_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 10.
MC_CGM.AC10_DC0.R = 0x80030000; //ENET_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).

MC_CGM.AC11_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 11.
MC_CGM.AC11_DC0.R = 0x80030000; //ENET_TIME_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).
}

[mkaradag1757]

@petervlna  Thanks for your interesting but I have still problems for this topic.

I have alread used calculator tool for sys clock init but it doesn't work.

Furthermore, I have tried led toggle with delay which I made little change in example project (https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-CGM-GHS614/ta-p/1120929). I observe that main clock works with 10-20 Mhz. How is it possible?

(I have changed only main and SIUL2_Init functions)

/*******************************************************************************
* Freescale Semiconductor Inc.
* (c) Copyright 2014 Freescale Semiconductor, Inc.
* ALL RIGHTS RESERVED.
********************************************************************************
Services performed by FREESCALE in this matter are performed AS IS and without
any warranty. CUSTOMER retains the final decision relative to the total design
and functionality of the end product. FREESCALE neither guarantees nor will be
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or actions by anyone on account of any damage, or injury, whether commercial,
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of the advise or assistance supplied CUSTOMER in connection with product,
services or goods supplied under this Agreement.
********************************************************************************
* File:             main.c
* Owner:            b21190(Vlna Peter)
* Version:          1.0
* Date:             Oct-22-2014
* Classification:   General Business Information
* Brief:            DRUN mode with max core frequency(200MHz) generated from PPL0
********************************************************************************
********************************************************************************
* Detailed Description:
*
*
* ------------------------------------------------------------------------------
* Test HW:  MPC57xx
* Maskset:  1N65H
* Target :  internal_FLASH
* Fsys:     200 MHz PLL with 40 MHz crystal reference
*
*
********************************************************************************
Revision History:
1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version
*******************************************************************************/

/*******************************************************************************
* Includes
*******************************************************************************/
#include "MPC5744P.h"

/*******************************************************************************
* Constants and macros
*******************************************************************************/
#define 	DRUN_MODE 	0x3

/*******************************************************************************
* External objects
*******************************************************************************/

/*******************************************************************************
* Global variables
*******************************************************************************/


/*******************************************************************************
* Local functions
*******************************************************************************/

/*******************************************************************************
Function Name : Sys_Init
Engineer      : b21190
Date          : Apr-04-2016
Parameters    : NONE
Modifies      : NONE
Returns       : NONE
Notes         : Clock settings
Issues        : NONE
*******************************************************************************/
void Sys_Init(void)
{
    //Enable external oscilator
    MC_ME.DRUN_MC.B.XOSCON = 1;

    // Set PLL0 to 200MHz
    PLLDIG.PLL0CR.B.CLKCFG = 1;		    //Bypass mode PLL0 on
    // RFDPHI1 = 10, RFDPHI = 2, PREDIV = 2, MFD = 14
    PLLDIG.PLL0DV.R = 0x50000000 |0x00020000 |0x00002000 |0x0014 ; //predefined PLL0 divider register

    // Set PPL0 as system clock
    MC_ME.DRUN_MC.B.PLL0ON = 1;             //Enable PLL0 for DRUN mode
    MC_ME.DRUN_MC.B.SYSCLK = 0x2;

    //  System clock dividers //

    // Enable system clock divider /4 -> 50MHz
    // (PBRIDGE_0, PBRIDGE_1, SIPI, DMA_CH_MUX) - Use only odd DIV values(2,4,etc..)
    //            Enable divider | divide by 4
    MC_CGM.SC_DC0.R = 0x80000000 | 0x30000;


    //  AUX_0 clock dividers //

    MC_CGM.AC0_SC.B.SELCTL =0x2;		//connect PLL0 to AXU_0

    // MOTC_CLK clock devider = 3 -> 200MHz/2 = 100MHz
    //             Enable divider | divide by 2
    MC_CGM.AC0_DC0.R = 0x80000000 | 0x10000;

    // SGEN_CLK clock devider = 10 -> 200MHz/10 = 20MHz
    //             Enable divider | divide by 10
    MC_CGM.AC0_DC1.R = 0x80000000 | 0xA0000;

    // SAR ADC clock devider = 3 -> 200MHz/3 = 66.6MHz
    //             Enable divider | divide by 3
    MC_CGM.AC0_DC2.R = 0x80000000 | 0x20000;


    //  AUX_1 clock dividers //

    // FRAY_CLK clock devider = 5 -> 200MHz/5 = 40MHz
    //             Enable divider | divide by 5
    MC_CGM.AC1_DC0.R = 0x80000000 | 0x40000;

    // SENT_CLK clock devider = 3 -> 200MHz/3 = 66.6MHz
    //             Enable divider | divide by 3
    MC_CGM.AC1_DC1.R = 0x80000000 | 0x20000;


    //  AUX_2 clock dividers //

    // CAN_CLK clock devider = 5 -> 200MHz/5 = 40MHz
    //             Enable divider | divide by 5
    MC_CGM.AC2_DC0.R = 0x80000000 | 0x40000;


    //  AUX_3 clock dividers //

    //	AUX Clock Selector 3 setup - source for PLL0 module
    MC_CGM.AC3_SC.B.SELCTL =1;			//connect (8..40MHz) XTALL to the PLL0 input
                           //0=IRC   1=XOSC


    //  AUX_4 clock dividers //

    //AUX Clock Selector 4 setup - source for PLL1 module
    MC_CGM.AC4_SC.B.SELCTL =3;			//connect PLL0 to AUX4


    //  AUX_5 clock dividers //

    MC_CGM.AC5_SC.B.SELCTL =0x2;		//connect PLL0 to AXU_5

    // LFAST PLL clock devider = 10 -> 200MHz/10 = 20MHz
    //            Enable divider | divide by 10
    MC_CGM.AC5_DC0.R = 0x80000000 | 0x90000;


    //  AUX_6 clock dividers //

    MC_CGM.AC6_SC.R = 0x02000000;           	//connect PPL0 to AUX_6
    // CLKOUT_0 clock devider = 20 -> 200MHz/20 = 10MHz
    //            Enable divider | divide by 20
    MC_CGM.AC6_DC0.R = 0x80000000 | 0x140000;


    //  AUX_10 clock dividers //

    MC_CGM.AC10_SC.R = 0x02000000;           	//connect PPL0 to AUX_10

    // ENET_CLK clock devider = 4 -> 200MHz/4 = 50MHz
    //            Enable divider | divide by 4
    MC_CGM.AC10_DC0.R = 0x80000000 | 0x30000;


    //  AUX_11 clock dividers //

    MC_CGM.AC11_SC.R = 0x02000000;           	//connect PPL0 to AUX_11

    // ENET_TIME_CLK clock devider = 4 -> 200MHz/4 = 50MHz
    //            Enable divider | divide by 4
    MC_CGM.AC11_DC0.R = 0x80000000 | 0x30000;

    //Mode transition to apply the PLL0 setup and set Normal mode with PLL running
    MC_ME.MCTL.R = 0x30005AF0;              //DRUN Mode & Key
    MC_ME.MCTL.R = 0x3000A50F;              //DRUN Mode & Key

    while(!MC_ME.GS.B.S_PLL0);              //ME_GS Wait for PLL stabilization.
    while(MC_ME.GS.B.S_MTRANS);             //Waiting for end of transaction
    while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE);  // ME_GS Check DRUN mode has successfully been entered


    MC_ME.DRUN_MC.B.PLL1ON = 1;             //Enable PLL1 for DRUN mode

    //Configure RunPeripheralConfiguration registers in ME_RUN_PC0
    MC_ME.RUN_PC[0].B.DRUN = 1;             //Enable DRUN mode for all peripherals using ME_RUN_PC[0]
    // Set PLL1 to 200 MHz with 40MHz XOSC reference
    PLLDIG.PLL1DV.R = 0x00020014;	     // MFD = 20, RFDPHI = 2

    //Mode transition to apply the PLL0 setup and set Normal mode with PLL running
    MC_ME.MCTL.R = 0x30005AF0;              //DRUN Mode & Key
    MC_ME.MCTL.R = 0x3000A50F;              //DRUN Mode & Key

    while(!MC_ME.GS.B.S_PLL0);              //ME_GS Wait for PLL stabilization.
    while(MC_ME.GS.B.S_MTRANS);             //Waiting for end of transaction
    while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE);  // ME_GS Check DRUN mode has successfully been entered

}//Sys_Init

/*******************************************************************************
Function Name : SUIL2_Init
Engineer      : b21190
Date          : Oct-22-2014
Parameters    : NONE
Modifies      : NONE
Returns       : NONE
Notes         : SIUL2 initialization (ports), setting PB6(B9) as output for clock measurement
Issues        : NONE
*******************************************************************************/
void SUIL2_Init(void)
{
   SIUL2.MSCR[22].R = 0x22800001;   	/* PB6 as CLK_OUT (on EVB it is B9)*/
   SIUL2.MSCR[43].R = 0x22800000; 	//PC[11] GPIO - Red LED
   SIUL2.GPDO[43].R = 1;
}//SUIL2_Init

/*******************************************************************************
* Global functions
*******************************************************************************/
int main (void)
{
  int i=0;
  Sys_Init();
  SUIL2_Init();

  while(1)
  {
	  while(i++<10000000){} // if sys clk work 200mhz red led should toggle approximately 20 hz. But it works 1 hz. How is it possible?   
	  SIUL2.GPDO[43].R = ~SIUL2.GPDO[43].R; // RED LED TOGGLE
	  i=0;
  }
}//main

best regards.

[petervlna]

Hello,

Sure, please have a look at following configuration in example SW:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-CGM-GHS614/ta-p/1120929

Furthermore we have calculator tool which can help you to configure clock:

https://community.nxp.com/docs/DOC-328021

I can see that you have on pin 200MHz

MC_CGM.AC6_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 6.
MC_CGM.AC6_DC0.R = 0x80000000; //CLKOUT0: Enabled at Auxiliary Clock 6 divided by 1 (200 MHz).

Have in mind that pin is capable max 40Mhz, best it to have 20MHz or less for accurate clock in pin.

For example I divide output clock by 20

// AUX_6 clock dividers //

MC_CGM.AC6_SC.R = 0x02000000; //connect PPL0 to AUX_6
// CLKOUT_0 clock devider = 20 -> 200MHz/20 = 10MHz
// Enable divider | divide by 20
MC_CGM.AC6_DC0.R = 0x80000000 | 0x140000;

best regards,

Peter