MPC5606B : EMIOS Channel configured as Output Pulse Width and Frequency Modulation Buffered Issue

[raghavendrapura]

Hello,

For our project we have enabled a EMIOS channel to be used as Output Pulse Width and Frequency Modulation Buffered. We are using RappiD tool for configuration.

Below is the initialization code generated by for a EMIOS channel :

-------------------------------------------------------------------------------------------------------------------------------

/* ----------------------------------------------------------- */

/*    EMIOS Module Configuration Register (EMIOS_MCR)            */

/* ----------------------------------------------------------- */

   EMIOS_0.MCR.R = 0x14000000;

            /* Module : Enable    */

            /* Global Freeze: Disabled                  */

            /* Global Time Base Enable: Yes             */

            /* Global Prescaler Enable: Yes             */

            /* Global Prescaler Value:   1              */

/* ----------------------------------------------------------- */

/* EMIOS Output Update Disable Register (EMIOS_OUDR)           */

/* ----------------------------------------------------------- */

  EMIOS_0.OUDR.R = 0x00000000;

            /* Channel n output is Enabled  */

            /*   n = 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 */

/* ----------------------------------------------------------- */

/* EMIOS Channel Disable Register  (EMIOS_UCDIS)           */

/* ----------------------------------------------------------- */

  EMIOS_0.UCDIS.R = 0x00000000;

            /* Channel n is Enabled  */

            /*   n = 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31, */

/* ----------------------------------------------------------- */

/*    Unified Channel 02 Registers                               */

/* ----------------------------------------------------------- */

  EMIOS_0.CH[2].CADR.R = 0x00007D00;

            /*  [16-31]  Channel eMIOS_0_CADR2 Data Register - eMIOS_0_CADR2 : Value = 32000*/

  EMIOS_0.CH[2].CBDR.R = 0x0000FA00;

            /*  [16-31]  Channel eMIOS_0_CBDR2 Data Register - eMIOS_0_CBDR2 : Value = 64000*/

  EMIOS_0.CH[2].CCR.R = 0x020006D8;

            /* Channel Control Register                 */

            /* Freeze Enable : Normal operation         */

            /* Prescaler Divide Ratio : 1             */

            /* Prescaler Enable : Enable                */

            /* Flag generation Request: Assigned to Interrupt */

            /* Input Filter: Not Applicable                */

            /* Filter clock select : Prescaler clock    */

            /* Flag Enable : IRQ/DMA not generated      */

            /* Force Match A : Disabled                 */

            /* Force Match B : Disabled                 */

            /* Bus Select : Internal counter                */

            /* Edge Selection Bit :Not Applicable                 */

            /* Edge Polarity :Set on Match A                   */

            /* Mode : Output Pulse Width and Frequency M*/

            /* odulation Buffered                       */

---------------------------------------------------------------------------------------------------------------------------------------

System Clock is 64MHZ and pheripheral clock is also 64Mhz for Emios.

The above example generates a PWM period of 1ms with 50% duty cycle.

But when i change the values of PWM to different value then it does not reflect the new value. It is always with 1ms and 50% duty cycle.

For changing to new value i only update CADR and CBDR registers by calling in the application with new duty cycle and period. But new values are not at all accepted by the EMIOS module.

I verified it on the CRO

For my application i am supposed to generate varying duty cycle and frequency. But i am not able to change it with above settings. Kindly advice how i could achieve variable duty cycle and frequency using EMIOS module.

Regards,

Raghavendra P

[martin_kovar]

Hi,

I am sending you simple code which shows, how to change frequency and duty cycle.

At first it is better to use some prescaler, because CADR and CBDR has 16 bits and without prescaler you sometimes not able to create required frequency.

Look at the attached example and if have any questions feel free to write me back.

Regards,

Martin