MPC55XX:RD_WR/ or OE/ ?

[ypchen]

<MPC5553_MPC5554_RM>,12.4.2 External Bus Operations

...To facilitate asynchronous write support, the EBI keeps driving valid write data on the data bus until 1 clock after the rising edge where RD_WR/ (and WE for chip select accesses) are negated.

In my project,the RD_WR/ connect to the 74LVTH16245's direction-control (DIR) .When RD_WR/ is low,data transmission from the B bus ( MPC data bus)to the A bus(Memory data bus).In Write Cycle(CS Access) ,because RD_WR/ negated earlier ,the 74LVTH16245 does not keep driving valid data on the A bus after the rising edge of RD_WR/ (the  A bus data and the WE[0:3]/ are negated in the same time)

Can I use OE/ instead  RD_WR/ ( OE/ connect to the DIR)?What do I need to pay attention?

[davidtosenovjan · Accepted solution]

If your project use CS access only, then OE/ could be used instead RD_WR/. Pay attention to setup and hold time during read cycle. Note that OE/ is active low signal whilst RD_WR/ is active high in the context of their functionality.