Hi expert,
I am working well through document AN4365 Qorivva MPC56xx Flash Programming Through Nexus JTAG. But when I debug MPC55xx using document AN3283 MPC5500 Flash Programming Through Nexus JTAG, I met some problems.
When GPR write Access, Single Step return back OnCE Status Register is 0x309, not 0x209. Before single step, the IR of cpuscr access used LWZ R31 ( 0x53FE0000 ) , it was the same with MPC56xx.
Could you give me some advices? Is it the Instruction Register (IR) right ( 0x53FE0000 ) to MPC55xx?
Hi,
if I can remember, this worked on my side on MPC55xx (testing script for Lauterbach debugger):
;scan in OCMD - select CPUSCR register
JTAG.SHIFTTMS 1 1 0 0 ;enter Shift-IR
JTAG.SHIFTREG 0 0 0 0 1 0 0 0 0 0 ;CPUSCR register (Register Select 0b001_0000, least significant bit first)
JTAG.SHIFTTMS 1 0 ;return to run-test/idle
;write CPUSCR
JTAG.SHIFTTMS 1 0 0 ;enter Shift-DR
JTAG.SHIFTTDI %Long 0x40000100 ;WBBRlow - this value will replace "X" in e_lwz instruction
JTAG.SHIFTTDI %Long 0x00000000 ;WBBRhigh
JTAG.SHIFTTDI %Long 0x00000000 ;MSR
JTAG.SHIFTTDI %Long 0x40000000 ;PC - address to some valid memory
JTAG.SHIFTTDI %Long 0x53E00000 ;IR - opcode for instruction e_lwz r31,0(X)
JTAG.SHIFTREG %Long 0x00000402 ;CTL - set FFRA bit and IRSTAT8 bit
JTAG.SHIFTTMS 1 0 ;return to run-test/idle
;call function which performs single step over instruction loaded in CPUSCR
GOSUB JTAG_SingleStep
Which address do you read? Do you use WBBRlow? Is FFRA set?
Did you try to read another address?
Regards,
Lukas
Yes, after entering to debug mode (0x209), I set OCR, DBCR0, DBSR registers.
Then I can read CPUSCR register, the value are:
wbbrlow = 0x0
wbbrhigh =0x0
init_msr = 0x0
init_pc = 0xFFFFFFFC
init_ir = 0x79FFF064
init_ctl = 0x2
I used write_cpuscr function with your suggesting parameters or MPC56xx parameters, single setp return back 0x309, ERR bit error.
cpuscr_access(0x40000100, 0x0, 0x0, 0x40000000, 0x53E00000, 0x402, WR_CPUSCR);
single_step();
I try ram address 0x40000100, flash address 0x0, MIDR address 0xFFFE8004, the results were the same.
I can't find the err reason.
Only one idea now - is MMU configured? Can you read those addresses using Nexus RW access?
Regards,
Lukas