First, Power timing is ok.
Second,now when testing the CPU to communicate with DDR2 device, there will be a problem of incorrect communication data..
Could you please help to confirm whether the configuration of tDQSEN to 2.5 tCK is correct?
DDR2 part Number: ISSI IS43DR16320D-3DBI
DDR2 configuration: tCK = 5000PS, CL=3, T(READ PREAMBLE of DQS) = 1.0tCK.
Then refer to Table23 of MPC5125 DS and Table 11-3 of MPC5125 RM. I think it would be better to set tDQSEN to 2.75.
I have two questions:
1:How do I set the value of tDQSEN more appropriately? 2.5tCK or 2.75tCK?
2:In table 23 of MPC5125: the tDQSEN is from 2.5tCK to 3tCK+1500, and Note 5 below the table is described as follows:"The window position is given for tDQSEN = 2.5 tCK (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2 SDRAM device"
But, refer to table 11-3 of MPC5125: tDQSEN is 3tCK when RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0.It seems inconsistent with the tDQSEN=2.5tCK of Note 5
How should I understand the description of Note5?