MPC5125 reset failed from PORESET pin

[jimmyli]

Dears: there is a certain probability that the MPC5125 will not work properly after reset by PORESET pin, When tested under the condition of minus 40℃. After checking, it was found that the MPC5125 would get stuck in the UART initialization code,But we haven't pinpointed the exact wrong location yet.The problem will go away until the power supply is turned off and on again. Please help to analyze the cause of the failure. Thanks Software code flow is as follows, and UART initialization is in API driver: print2comInit(); #if(cpu_FAMILY==PPC) _WRS_ASM('' ''); vxSdaInit(); _WRS_ASM('' ''); #endif print2comInit(); ... Looking forward to your reply! Thanks again.

[Pavel]

Perhaps the MPC5125 PORESET is negated and power supply is not stable in this time.

Test your board using long time for PORESET assertion.

[jimmyli]

Hi Pavel,

      OK, I will try it as you said.

      Thanks.

[jimmyli]

Hi Pavel:

First, Power timing is ok.

Second,now when testing the CPU to communicate with DDR2 device, there will be a problem of incorrect communication data..

Could you please help to confirm whether the configuration of tDQSEN to 2.5 tCK is correct?

DDR2 part Number: ISSI IS43DR16320D-3DBI

DDR2 configuration: tCK = 5000PS, CL=3, T(READ PREAMBLE of DQS) = 1.0tCK.

Then refer to Table23 of MPC5125 DS and Table 11-3 of MPC5125 RM. I think it would be better to set tDQSEN to 2.75.

I have two questions:

1:How do I set the value of tDQSEN more appropriately? 2.5tCK or 2.75tCK?

2:In table 23 of MPC5125: the tDQSEN is from 2.5tCK to 3tCK+1500, and Note 5 below the table is described as follows:"The window position is given for tDQSEN = 2.5 tCK (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2 SDRAM device"

But, refer to table 11-3 of MPC5125: tDQSEN is 3tCK when RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0.It seems inconsistent with the tDQSEN=2.5tCK of Note 5

How should I understand the description of Note5?

Thanks