Hello,
I am using MPC5777C processor.
I am writing an MCAN driver and I "discovered" that seem that registers (not only BTP, but also some others) are changed between silicon and reference manual revisions.
RM rev 4:
RM rev 8:
I discovered that also from documentation coming from core IP (M_CAN) developer the situation it is exactly the same (there is only a little tracking in release notes: "Register FBTP renamed to DBTP and restructured")
Shall I cope with both version of M_CAN (using M_CAN_CREL)? (I see someone have proposed a patch for this on linux kernel: can: m_can: fix bitrate setup on latest silicon - Patchwork )
I guess why in the last revision of manual there is nothing that let me know that exist a older version of M_CAN in old MPC5777C...
By harvesting a little more I discovered exist two hardware maskset: 2N45H and 3N45H
And there is a pdf (MPC5777CRMAD.pdf) reporting (as a whole...) the older M_CAN peripheral chapter.
Are there others masksets?
What is the content of CREL register for both versions?
Hi,
Yes, the MCAN was revised in the latest maskset and the latest RM (rev8) describes the functionality and programming model of maskset 3N45H.
With some exceptions, this RM also describes maskset 2N45H. For information about 2N45H's differences from 3N45H, see the MPC5777C Reference Manual Addendum (http://www.nxp.com/assets/documents/data/en/reference-manuals/MPC5777CRMAD.pdf).
BR, Petr
Thank you for the confirmation.
For us this is a problem due to software validation...
Is it possibile to know the possible values of M_CAN_CREL register expected on MPC5777C? In the RM is only reported an "example" of the value (and it is the same in RM and RM addendum).
Thank you.
Hi,
below is CREL values for both masks...
2N45H: CREL = 0x30130506
3N45H: CREL = 0x32150320
The doc ticket will be raised to fix the RM.
BR, Petr