How can MPC5744 go into IVOR1 except ECC error?

[zhaoning]

Hi, NXP experts,

recently we are facing an IVOR1 problem. We know that  System RAM ECC event, Peripheral RAM ECC event and Internal FLASH ECC event can generate IVOR1 interrupt, and we can get these events from MEMU registers. But now we test that other event may also lead to an IVOR1 interrupt, for example, when I access an illegal address . But the MEMU register cannot capture these events. Is there a way to capture events that can cause IVOR1 interrupt through other registers?

[zhaoning]

Another requirement is that we have observed sporadic software jumps to the IVOR1 interrupt on the actual vehicle. We have ruled out ECC faults as the cause and are wondering if there is a way to determine what instructions were being executed before entering this function. In other words, we would like to identify which function's abnormal execution led to entering the IVOR1 interrupt. Since the issue is sporadic, we are unable to pinpoint it through debugging. Our proposed solution involves sending the address of the function being executed in IVOR through CAN messages to assist in our analysis of the problem. Is this method feasible? In IVOR1 interrupt service routine, how can we obtain the address of the instruction being executed before entering IVOR1? Are there any reference demos available for us?

thanks!!!

[davidtosenovjan]

It should be achievable. An address is stored in MCSRR0 register.

If you see example code of this appnote, you may see how to read MCSRR0 register within IVOR1 handler.

In the debugger you will see core registers within tab "All registers", section 'Exception_Handling_Control_Registers'

[zhaoning]

Yes, I noticed the assembly instructions in the demo, but it's possible that the demo was compiled using Green Hills, while I'm using S32 Design Studio for compilation. Due to the different compilers, when I tried placing the assembly code from the demo into my existing project and compiled it, I encountered errors. Is there a demo available in S32DS that showcases how to access these core registers?

Another question, I found how to obtain the value of a core register in S32DS on another post. MCSR is SPR 572. When I induce a PFLASH ECC fault and enter the IVOR1 function, I read MCSR through writing to the console command monitor spr 572t and get a value of 0x88008. However, this seems inconsistent with the register bit definitions in the manual (MAV bit not set to 1, but bit 19 which is a reserved bit set to 1). I would like to understand the reason behind this discrepancy.

[davidtosenovjan · Accepted solution]

Power Architecture uses numbering style that bits in registers are marked in reverse.

I am attaching an excel sheet that I have printed and stuck on the wall.

[zhaoning]

Thank you sir, you have solved all of my problems.

[davidtosenovjan]

Someone has ported one of these examples to S32DS, you may find it as an example code there.

[davidtosenovjan]

Pay attention to my appnote, section 8.1

https://www.nxp.com/docs/en/application-note/AN13179.pdf

It describes how to distinguish bus errors caused by ECC. But if there is no records in MEMU, reason may be other than ECC. Also other flags in MCSR may indicate other reasons of machine check exception.

It is needed to consult e200z4251n3 core documentation.

[zhaoning]

Hi,

I noticed there is a description of MCSR in the reference manual. I am wondering if we can read the value of MCSR in the EmbSys Registers window similar to reading peripheral registers, or in the Memory window? Do I need to write assembly code to access the data in this register? Is there any demo available for this? For instance, could I write the result of this register to a specific RAM memory location?