I've read the Reference Manual description of the CAN_RXFGMASK register, but I don't understand it. I find the PPC register bits always being number backwards compared to normal confusing which then leads on to not understanding how to programme this register.
I've looked at the example code for a few processors, but they unhelpfully set wide open masks and receive identifier zero. It would be far more helpful if those piece of code used a non-zero message identifier and did programme some masks.
So.. this register's bits are numbered 0-31 for msb-lsb. I'm going to be using format 'A' with a single mask. The description table in section 47.4.17 lists:
RTR = FGM[31] <--- is this the msb or lsb ?
IDE = FGM[30]
RXIDA = FGM[29:1] <-- is this really 1:29 to match with the 'backwards' numbering or 29:1 to match normal numbering ?
Reserved = FGM[0] <-- is this the msb or lsb ?
It would be far more helpful (to me) to show the three Filter Table Elements Formats as three variants of the register description instead of using the table due to the ambiguity about bit numbering.
James
Slightly earlier in the manual in section 47.4.5 another register has conflicting information as below:
This mixing of bit numbering is not helpful. Please resolve it. As per my previous comment, showing the register pictorially for the five cases could aid clarity.
James
Hi James,
yes, you are right. The bit alignment is not clear for those registers. The PowerPC notation is used for the registers, where 0 is MSB and 31 LSB. Sometimes bitfields use opposite direction in its description, but in this case the alignment should be clearly stated.
For example; same registers from MPC5744P RM
BR, Petr