Encountering IVOR12 after enabling SPE

[morrisli]

Hi all,

    We have a project that  on the MCU S32R372. The firmware work normally without issue with following target processor setting 

Then we changed target processor setting to enable SPE and change libraries as following,

The normal firmware became hanging in IVOR12, i.e. core watchdog ISR, while calling the callback function of CAN transmission ISR. The stack and disassembly code code was as following.

 We tried to check the CSRR0 and CSRR1  as suggested in the document “e200z760n3 Power Architecture® Core Reference Manual.” But the read out address for these two registers are 0x00000000, which could not found instruction address cause this issue.  Does any one have idea that why changing target configuration could cause error triggering of IVOR12 or how to find the root cause?

[petervlna]

Hello,

Could you share the output file with me. So I can test it here. Or more detailed analyze on the issue when IVOR is called.

But it is strange that your CSRR0/1 is not holding address /MSR. It looks like no IVOR12 is called. As the CSRRx is filled when the IVOR 12 is called.

The screen you have presented to me is most probably not IVOR12 handler.

regards,

Peter