D cache and SMPU lead to a memory exception in MPC5746C

[1045302770]

Hi, 

In my multi core project of MPC5746C, I need a cache inhibited memory region for inter-core communication, so I tried to use SMPU module. To test weather SMPU and cache can work together, I configured just one memory region descriptor(0x00000000 - 0xFFFFFFFF) and enabled all masters with write/read access right, the test result is as follows:

1. With cache enabled and SMPU not used, Z4 core and Z2 core runs normally.
2. With SMPU and cache disabled, Z4 core and Z2 core runs normally.
3. With SMPU and cache enabled, Z4 core runs normally, but there is a memory exception on Z2 core.

Since all masters has both read and write access(FMT = 0, SMPU_RD_W2_F0 = 0xFFFFFFFF), I'm confused that what's the reason for memory exception on Z2 core?

Best Regards!

Victor

[1045302770]

@lukaszadrapa  @davidtosenovjan Would you please give me some advice to solve this problem? I have tried to use SMPU and cache in a single core project(Z4), but there is still a read or write access control exception. Besides, is there any example code about SMPU of MPC5746C?

Looking forward for your reply!

Best Regards!

[davidtosenovjan]

SMPU and cache may used together, there is no conflict with such configuration.

[davidtosenovjan]

Following example codes exists, both prepared by colleague Lukas (currently on Christmas vacation):

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-GHS614/ta-p...

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-...

[1045302770]

Hi, @davidtosenovjan 

     Thanks for your reply. I used the method in the example with MPC5748G, and it works as expected. But it failed to run on MPC5746C. As I mentioned above, when I use cache and SMPU together, an exception occurs. Would you please share me an example code of SMPU and cache used for MPC5746C? Thanks a lot again!

[1045302770]

Hi, @davidtosenovjan ,@lukaszadrapa,

      Sorry, I forgot a message. 

      Smpu and cache works fine on MPC5748G, both single core project and multi core project.

      But on MPC5746C, only the single core project works fine, and for the multi core project, an exception occurs.

      Would you please give me some advice to solve this problem.

      Looking forward for your reply!