Hi:
Recently, I've installed the ls1028ardb edge 2.0 image onto the official evaluation board. However, through /sys/kernel/debug/mmc1/ios, I found that the actual clock of emmc is lower than expected. For example, even if the HS200 mode is set, the actual clock is only 83M. Could you please advise on how to adjust the actual clock of emmc?
clock: 200000000 Hz
actual clock: 83333333 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 9 (mmc HS200)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
已解决! 转到解答。
The actual driver has support for the HS400 mode.
Please use the LLDP 6.1.55, with this one you don't have to add any patch driver or modify the dts.
please note:
root@localhost:~# cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 150000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 10 (mmc HS400) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)
Technical parameters of the eSDHC HS400 mode are provided in the QorIQ LS1028A/LS1018A Data Sheet.
Due to A-011334: Limited clock dividers for HS400 mode, maximum SDHC_CLK frequency supported in HS400 (VDD=1.0v) mode is 150 MHz.
Hi:
Thank you for your reply. Currently, some customers have mass-produced according to this version of BSP, and they need to solve this problem based on the current version. Is there a similar patch available?