TBI Physical Address?

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TBI Physical Address?

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swanandpurankar
Contributor III

Hi,

I am configuring LS1021A in RMII mode. Initialization steps in Reference manual says -

Set MIIMADD = 0x0000_nn11 (TBICON, where nn=TBIPA)

When read through reference manual, I could understand that - In order to access any TBI register, I have to load it's address in MIIMADD register. But I don't understand what value I should assign to TBIPA.

TBI's Physical address is stored in TBIPA register.

How can I know TBI's Physical address?

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ufedor
NXP Employee
NXP Employee

The reason we have TBI registers mentioned in the initialization steps (for MII, RMII and RGMM) is because the  elastic FIFO reset logic is actually included in the internal TBI Phy logic. Hence a reset of the TBI Phy was added to the eTSEC/dTSEC recommended initialization sequence to ensure no "garbage" data would reside in the elastic FIFO during the controller's initialization.

We will add additional note in the next RM release to clarify this.

For eTSEC1 the TBIPA value should be non-zero and distinct from external PHYs addresses (if any).

For eTSEC2 and eTSEC3 the TBIPA value can be any in range 1-31.

Note that TBI PHY registers have to be accessed by means of MDIO registers belonging to the configured eTSEC.

For eTSEC2 MDIO range starts at 2D6_4000 address offset

For eTSEC3 MDIO range starts at 2DA_4000 address offset

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ufedor
NXP Employee
NXP Employee

The reason we have TBI registers mentioned in the initialization steps (for MII, RMII and RGMM) is because the  elastic FIFO reset logic is actually included in the internal TBI Phy logic. Hence a reset of the TBI Phy was added to the eTSEC/dTSEC recommended initialization sequence to ensure no "garbage" data would reside in the elastic FIFO during the controller's initialization.

We will add additional note in the next RM release to clarify this.

For eTSEC1 the TBIPA value should be non-zero and distinct from external PHYs addresses (if any).

For eTSEC2 and eTSEC3 the TBIPA value can be any in range 1-31.

Note that TBI PHY registers have to be accessed by means of MDIO registers belonging to the configured eTSEC.

For eTSEC2 MDIO range starts at 2D6_4000 address offset

For eTSEC3 MDIO range starts at 2DA_4000 address offset

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swanandpurankar
Contributor III

Means, Do I have to ignore these steps?

Additionally, If I have to access TBI registers, I will have to load TBIPA value... So what should I load it?

Or you mean to say TBI is not at all relevant to MII, RMII and RGMII modes? Then where it is required? 

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ufedor
NXP Employee
NXP Employee

Please see corrected response.

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swanandpurankar
Contributor III

Thanks for that... It resolved some confusion...

But is that means, Instead of MIIMADD registers mentioned in Initialization sequence, should I use eTSEC_MDIO_MIIMADD and so on?

ufedor wrote:

Note that TBI PHY registers have to be accessed by means of MDIO registers belonging to the configured eTSEC.

Or simply follow the initialization sequence as it is and after init, use eTSEC_MDIO_MIIMADD?

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ufedor
NXP Employee
NXP Employee

> Or simply follow the initialization sequence as it is and after init, use eTSEC_MDIO_MIIMADD?

Correct, eTSECn_MDIO_MIIMADD

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swanandpurankar
Contributor III

mmm... Let me reframe the question...

Do I need to use eTSEC_MDIO_MIIMADD in initialization seqeuence?

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ufedor
NXP Employee
NXP Employee

Yes - see note in the first response.