SERDES GEN 3 Speeds

[vanlandingham10]

The Ref man states that:

"PCIe Gen 3 speed support requires switching to second PLL so when Gen 3 is used
both SerDes PLL will be used by PCIe protocol."

Does this mean if I intend on using config 5577 for SERDES PORT 2 That I need to provide two separate external 100 MHZ refclks or can I just provide 1 external 100 MHz refclk and configure the internal mux to re-direct the 2nd pll to use the same external refclk?

[mrudangshelat-13]

Hi @vanlandingham10 

Which specific processor are you referring to?

Regards,
Mrudang Shelat

[vanlandingham10]

sorry the LS1046

[vanlandingham10]

I'd like to configure the SERDES ports to support 5577 and 1133. Will my clock scheme work?

[mrudangshelat-13]

Hi @vanlandingham10,

The clocking scheme looks fine.

Regards,
Mrudang Shelat

[vanlandingham10]

Okay so If SERDES2 is entirely used for pcie gen3 I can pass a single reference clock to each pll via the internal mux ?

[mrudangshelat-13]

Hi

Yes, you can configure SD2_REF_CLK1/SD2_REF_CLK1_B to both the PLL.

Regards,
Mrudang Shelat