LX2160x ts2phc cannot synchronize time between two clock domains

[Lixun]

Hi，

I am using the PTP function of the LX2160 and I have successfully generated a PTP device as shown in the image below

##phc_ctl /dev/ptp0 cap
capabilities:
249999999 maximum frequency adjustment (ppb)
2 programable alarms
2 external time stamp channels
3 programmable periodic signals
0 configurable input/output pins
has pulse per second support
doesn't have cross timestamping support

##cat /sys/class/ptp/ptp0/clock_nam
DPAA2 PTP Clock

At the same time, there is another PHC device (ptp1) on my system, which generates PPS and outputs to DPAA2 PTP CLOCK (ptp0).

I am using ts2phc to sync the two devices, but this seems to have some drawbacks, the output is as follows.

ts2phc[4591.981]: /dev/ptp0 extts index 0 at 16741.999998770 corr 0 src 16742.1177734 diff -1230
ts2phc[4591.981]: /dev/ptp0 master offset -1230 s1 freq +0
ts2phc[4592.982]: /dev/ptp0 extts index 0 at 16742.999998660 corr 0 src 16743.1177600 diff -1340
ts2phc[4592.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4593.982]: /dev/ptp0 extts index 0 at 16743.999998660 corr 0 src 16744.1177618 diff -1340
ts2phc[4593.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4594.982]: /dev/ptp0 extts index 0 at 16744.999998660 corr 0 src 16745.1177454 diff -1340
ts2phc[4594.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4595.982]: /dev/ptp0 extts index 0 at 16745.999998740 corr 0 src 16746.1177470 diff -1260
ts2phc[4595.982]: /dev/ptp0 master offset -1260 s1 freq +0
ts2phc[4596.982]: /dev/ptp0 extts index 0 at 16746.999998660 corr 0 src 16747.1177338 diff -1340
ts2phc[4596.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4597.982]: /dev/ptp0 extts index 0 at 16747.999998660 corr 0 src 16748.1177294 diff -1340
ts2phc[4597.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4598.982]: /dev/ptp0 extts index 0 at 16748.999998670 corr 0 src 16749.1177250 diff -1330
ts2phc[4598.982]: /dev/ptp0 master offset -1330 s1 freq +0
ts2phc[4599.982]: /dev/ptp0 extts index 0 at 16749.999998660 corr 0 src 16750.1177116 diff -1340
ts2phc[4599.982]: /dev/ptp0 master offset -1340 s1 freq +0
ts2phc[4600.982]: /dev/ptp0 extts index 0 at 16750.999998740 corr 0 src 16751.1177014 diff -1260
ts2phc[4600.982]: /dev/ptp0 master offset -1260 s1 freq +0

I can never completely eliminate the deviation between them and enter the S2 state

For comparison, I used another PHY device on the board as ptp0, which is a PHY chip with TSU functionality.

phy-ptp0 and ptp1 can synchronize normally, as shown in the figure below.

The device tree of my DPAA2 PTP CLOCK is configured as follows

ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;
clocks = <&clockgen 4 1>;
little-endian;
fsl,extts-fifo;
fsl,cksel = <0>;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <512>;
fsl,tmr-add = <0xcccccccd>;
fsl,tmr-fiper1 = <999999990>;
fsl,tmr-fiper2 = <99990>;
fsl,max-adj = <249999999>;
};

May I ask what caused this situation?

Is it the configuration of the DPAA2 PTP CLOCK or the hardware connection problem?Looking forward to your reply

[SebastianG]

Hi @Lixun,

Talking to another team member, the issue is detailed in the following response:

----

According to your log: freq = 0, that means PTP clock will never be adjusted, that's why the clock offset value never converge, so Could you please provide me the following information:
1) full testing log, include the ts2phc configuration file
2) Any modification of the ts2phc software made by customer?
2) LSDK version and Linuxptp version? And It is suggested to used linuxptp software from LSDK. NXP has several patches for linuxptp and not upstreamed.

----

Regards,

Sebastian

[SebastianG]

Hello @Lixun ,

I'm working on your question, When I have any update I will let you know

Regards

[Lixun]

Thanks for your support, I synced some of my findings. I find that ptp_qoriq_adjtime in the DPAA2 PTP driver directly reads and writes the register first. This process causes delay, which leads to this deviation. Therefore, I ported a timercounter function, which is used by other PHC drivers, to implement adjtime using timecounter_read, which seems to have solved the problem.I think this is a defect of DPAA2 PTP driver, please check it.